1/* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12#define CONFIG_SYS_FSL_CLK 13 14/* 15 * Size of malloc() pool 16 */ 17#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22#define CONFIG_SYS_CLK_FREQ 100000000 23#define CONFIG_DDR_CLK_FREQ 100000000 24 25/* 26 * DDR: 800 MHz ( 1600 MT/s data rate ) 27 */ 28 29#define DDR_SDRAM_CFG 0x470c0008 30#define DDR_CS0_BNDS 0x008000bf 31#define DDR_CS0_CONFIG 0x80014302 32#define DDR_TIMING_CFG_0 0x50550004 33#define DDR_TIMING_CFG_1 0xbcb38c56 34#define DDR_TIMING_CFG_2 0x0040d120 35#define DDR_TIMING_CFG_3 0x010e1000 36#define DDR_TIMING_CFG_4 0x00000001 37#define DDR_TIMING_CFG_5 0x03401400 38#define DDR_SDRAM_CFG_2 0x00401010 39#define DDR_SDRAM_MODE 0x00061c60 40#define DDR_SDRAM_MODE_2 0x00180000 41#define DDR_SDRAM_INTERVAL 0x18600618 42#define DDR_DDR_WRLVL_CNTL 0x8655f605 43#define DDR_DDR_WRLVL_CNTL_2 0x05060607 44#define DDR_DDR_WRLVL_CNTL_3 0x05050505 45#define DDR_DDR_CDR1 0x80040000 46#define DDR_DDR_CDR2 0x00000001 47#define DDR_SDRAM_CLK_CNTL 0x02000000 48#define DDR_DDR_ZQ_CNTL 0x89080600 49#define DDR_CS0_CONFIG_2 0 50#define DDR_SDRAM_CFG_MEM_EN 0x80000000 51#define SDRAM_CFG2_D_INIT 0x00000010 52#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53#define SDRAM_CFG2_FRC_SR 0x80000000 54#define SDRAM_CFG_BI 0x00000001 55 56#ifdef CONFIG_RAMBOOT_PBL 57#define CONFIG_SYS_FSL_PBL_PBI \ 58 board/freescale/ls1021aiot/ls102xa_pbi.cfg 59#endif 60 61#ifdef CONFIG_SD_BOOT 62#define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 64#define CONFIG_SPL_FRAMEWORK 65#define CONFIG_SPL_LIBCOMMON_SUPPORT 66#define CONFIG_SPL_LIBGENERIC_SUPPORT 67#define CONFIG_SPL_ENV_SUPPORT 68#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 69#define CONFIG_SPL_I2C_SUPPORT 70#define CONFIG_SPL_WATCHDOG_SUPPORT 71#define CONFIG_SPL_SERIAL_SUPPORT 72#define CONFIG_SPL_MMC_SUPPORT 73#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 74 75#define CONFIG_SPL_TEXT_BASE 0x10000000 76#define CONFIG_SPL_MAX_SIZE 0x1a000 77#define CONFIG_SPL_STACK 0x1001d000 78#define CONFIG_SPL_PAD_TO 0x1c000 79#define CONFIG_SYS_TEXT_BASE 0x82000000 80 81#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 82 CONFIG_SYS_MONITOR_LEN) 83#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 84#define CONFIG_SPL_BSS_START_ADDR 0x80100000 85#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 86#define CONFIG_SYS_MONITOR_LEN 0x80000 87#endif 88 89#ifdef CONFIG_QSPI_BOOT 90#define CONFIG_SYS_TEXT_BASE 0x40010000 91#endif 92 93#define CONFIG_NR_DRAM_BANKS 1 94 95#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 96#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 97 98/* 99 * Serial Port 100 */ 101#define CONFIG_CONS_INDEX 1 102#define CONFIG_SYS_NS16550_SERIAL 103#define CONFIG_SYS_NS16550_REG_SIZE 1 104#define CONFIG_SYS_NS16550_CLK get_serial_clock() 105 106/* 107 * I2C 108 */ 109#define CONFIG_CMD_I2C 110#define CONFIG_SYS_I2C 111#define CONFIG_SYS_I2C_MXC 112#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 113#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 114#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 115 116/* EEPROM */ 117#define CONFIG_ID_EEPROM 118#define CONFIG_SYS_I2C_EEPROM_NXID 119#define CONFIG_SYS_EEPROM_BUS_NUM 0 120#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 122 123/* 124 * MMC 125 */ 126#define CONFIG_CMD_MMC 127#define CONFIG_FSL_ESDHC 128 129/* SATA */ 130#define CONFIG_LIBATA 131#define CONFIG_SCSI_AHCI 132#define CONFIG_SCSI_AHCI_PLAT 133#ifndef PCI_DEVICE_ID_FREESCALE_AHCI 134#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 135#endif 136#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 137 PCI_DEVICE_ID_FREESCALE_AHCI} 138 139#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 140#define CONFIG_SYS_SCSI_MAX_LUN 1 141#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 142 CONFIG_SYS_SCSI_MAX_LUN) 143 144/* SPI */ 145#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 146#define CONFIG_SPI_FLASH_SPANSION 147 148/* QSPI */ 149#define QSPI0_AMBA_BASE 0x40000000 150#define FSL_QSPI_FLASH_SIZE (1 << 24) 151#define FSL_QSPI_FLASH_NUM 2 152#define CONFIG_SPI_FLASH_BAR 153#define CONFIG_SPI_FLASH_SPANSION 154#endif 155 156/* DM SPI */ 157#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 158#define CONFIG_CMD_SF 159#define CONFIG_DM_SPI_FLASH 160#endif 161 162/* 163 * eTSEC 164 */ 165#define CONFIG_TSEC_ENET 166 167#ifdef CONFIG_TSEC_ENET 168#define CONFIG_MII 169#define CONFIG_MII_DEFAULT_TSEC 1 170#define CONFIG_TSEC1 1 171#define CONFIG_TSEC1_NAME "eTSEC1" 172#define CONFIG_TSEC2 1 173#define CONFIG_TSEC2_NAME "eTSEC2" 174 175#define TSEC1_PHY_ADDR 1 176#define TSEC2_PHY_ADDR 3 177 178#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 179#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 180 181#define TSEC1_PHYIDX 0 182#define TSEC2_PHYIDX 0 183 184#define CONFIG_ETHPRIME "eTSEC2" 185 186#define CONFIG_PHY_ATHEROS 187 188#define CONFIG_HAS_ETH0 189#define CONFIG_HAS_ETH1 190#define CONFIG_HAS_ETH2 191#endif 192 193/* PCIe */ 194#define CONFIG_PCIE1 /* PCIE controler 1 */ 195#define CONFIG_PCIE2 /* PCIE controler 2 */ 196 197#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 198 199#ifdef CONFIG_PCI 200#define CONFIG_PCI_SCAN_SHOW 201#endif 202 203#define CONFIG_CMD_PING 204#define CONFIG_CMD_DHCP 205#define CONFIG_CMD_MII 206 207#define CONFIG_CMDLINE_TAG 208#define CONFIG_CMDLINE_EDITING 209 210#define CONFIG_PEN_ADDR_BIG_ENDIAN 211#define CONFIG_LAYERSCAPE_NS_ACCESS 212#define CONFIG_SMP_PEN_ADDR 0x01ee0200 213#define COUNTER_FREQUENCY 12500000 214 215#define CONFIG_HWCONFIG 216#define HWCONFIG_BUFFER_SIZE 256 217 218#define CONFIG_FSL_DEVICE_DISABLE 219 220#define CONFIG_EXTRA_ENV_SETTINGS \ 221 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 222"initrd_high=0xffffffff\0" \ 223"fdt_high=0xffffffff\0" 224 225/* 226 * Miscellaneous configurable options 227 */ 228#define CONFIG_SYS_LONGHELP /* undef to save memory */ 229#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 230#define CONFIG_AUTO_COMPLETE 231 232#define CONFIG_CMD_GREPENV 233#define CONFIG_CMD_MEMINFO 234 235#define CONFIG_SYS_LOAD_ADDR 0x82000000 236 237#define CONFIG_LS102XA_STREAM_ID 238 239#define CONFIG_SYS_INIT_SP_OFFSET \ 240 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 241#define CONFIG_SYS_INIT_SP_ADDR \ 242 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 243 244#ifdef CONFIG_SPL_BUILD 245#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 246#else 247/* start of monitor */ 248#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 249#endif 250 251#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 252 253/* 254 * Environment 255 */ 256 257#define CONFIG_ENV_OVERWRITE 258 259#if defined(CONFIG_SD_BOOT) 260#define CONFIG_ENV_OFFSET 0x100000 261#define CONFIG_SYS_MMC_ENV_DEV 0 262#define CONFIG_ENV_SIZE 0x2000 263#elif defined(CONFIG_QSPI_BOOT) 264#define CONFIG_ENV_SIZE 0x2000 265#define CONFIG_ENV_OFFSET 0x100000 266#define CONFIG_ENV_SECT_SIZE 0x10000 267#endif 268 269#define CONFIG_OF_BOARD_SETUP 270#define CONFIG_OF_STDOUT_VIA_ALIAS 271 272#define CONFIG_MISC_INIT_R 273 274#include <asm/fsl_secure_boot.h> 275 276#endif 277