1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __LS1043AQDS_H__ 8#define __LS1043AQDS_H__ 9 10#include "ls1043a_common.h" 11 12#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13#define CONFIG_SYS_TEXT_BASE 0x82000000 14#elif defined(CONFIG_QSPI_BOOT) 15#define CONFIG_SYS_TEXT_BASE 0x40100000 16#else 17#define CONFIG_SYS_TEXT_BASE 0x60100000 18#endif 19 20#ifndef __ASSEMBLY__ 21unsigned long get_board_sys_clk(void); 22unsigned long get_board_ddr_clk(void); 23#endif 24 25#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28#define CONFIG_SKIP_LOWLEVEL_INIT 29 30#define CONFIG_LAYERSCAPE_NS_ACCESS 31 32#define CONFIG_DIMM_SLOTS_PER_CTLR 1 33/* Physical Memory Map */ 34#define CONFIG_CHIP_SELECTS_PER_CTRL 4 35#define CONFIG_NR_DRAM_BANKS 2 36 37#define CONFIG_DDR_SPD 38#define SPD_EEPROM_ADDRESS 0x51 39#define CONFIG_SYS_SPD_BUS_NUM 0 40 41#ifndef CONFIG_SPL 42#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43#endif 44 45#define CONFIG_DDR_ECC 46#ifdef CONFIG_DDR_ECC 47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49#endif 50 51#ifdef CONFIG_SYS_DPAA_FMAN 52#define CONFIG_FMAN_ENET 53#define CONFIG_PHY_VITESSE 54#define CONFIG_PHY_REALTEK 55#define CONFIG_PHYLIB_10G 56#define RGMII_PHY1_ADDR 0x1 57#define RGMII_PHY2_ADDR 0x2 58#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 59#define SGMII_CARD_PORT2_PHY_ADDR 0x1D 60#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 61#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 62/* PHY address on QSGMII riser card on slot 1 */ 63#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 64#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 65#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 66#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 67/* PHY address on QSGMII riser card on slot 2 */ 68#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 69#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 70#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 71#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 72#endif 73 74#ifdef CONFIG_RAMBOOT_PBL 75#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 76#endif 77 78#ifdef CONFIG_NAND_BOOT 79#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 80#endif 81 82#ifdef CONFIG_SD_BOOT 83#ifdef CONFIG_SD_BOOT_QSPI 84#define CONFIG_SYS_FSL_PBL_RCW \ 85 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 86#else 87#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 88#endif 89#endif 90 91/* LPUART */ 92#ifdef CONFIG_LPUART 93#define CONFIG_LPUART_32B_REG 94#endif 95 96/* SATA */ 97#define CONFIG_LIBATA 98#define CONFIG_SCSI_AHCI 99#define CONFIG_SCSI_AHCI_PLAT 100 101/* EEPROM */ 102#define CONFIG_ID_EEPROM 103#define CONFIG_SYS_I2C_EEPROM_NXID 104#define CONFIG_SYS_EEPROM_BUS_NUM 0 105#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 106#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 107#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 108#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 109 110#define CONFIG_SYS_SATA AHCI_BASE_ADDR 111 112#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 113#define CONFIG_SYS_SCSI_MAX_LUN 1 114#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 115 CONFIG_SYS_SCSI_MAX_LUN) 116 117/* 118 * IFC Definitions 119 */ 120#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 121#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 122#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 123 CSPR_PORT_SIZE_16 | \ 124 CSPR_MSEL_NOR | \ 125 CSPR_V) 126#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 127#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 128 + 0x8000000) | \ 129 CSPR_PORT_SIZE_16 | \ 130 CSPR_MSEL_NOR | \ 131 CSPR_V) 132#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 133 134#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 135 CSOR_NOR_TRHZ_80) 136#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 137 FTIM0_NOR_TEADC(0x5) | \ 138 FTIM0_NOR_TEAHC(0x5)) 139#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 140 FTIM1_NOR_TRAD_NOR(0x1a) | \ 141 FTIM1_NOR_TSEQRAD_NOR(0x13)) 142#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 143 FTIM2_NOR_TCH(0x4) | \ 144 FTIM2_NOR_TWPH(0xe) | \ 145 FTIM2_NOR_TWP(0x1c)) 146#define CONFIG_SYS_NOR_FTIM3 0 147 148#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 149#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 150#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153#define CONFIG_SYS_FLASH_EMPTY_INFO 154#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 155 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 156 157#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 158#define CONFIG_SYS_WRITE_SWAPPED_DATA 159 160/* 161 * NAND Flash Definitions 162 */ 163#define CONFIG_NAND_FSL_IFC 164 165#define CONFIG_SYS_NAND_BASE 0x7e800000 166#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 167 168#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 169 170#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 171 | CSPR_PORT_SIZE_8 \ 172 | CSPR_MSEL_NAND \ 173 | CSPR_V) 174#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 175#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 176 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 177 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 178 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 179 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 180 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 181 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 182 183#define CONFIG_SYS_NAND_ONFI_DETECTION 184 185#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 186 FTIM0_NAND_TWP(0x18) | \ 187 FTIM0_NAND_TWCHT(0x7) | \ 188 FTIM0_NAND_TWH(0xa)) 189#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 190 FTIM1_NAND_TWBE(0x39) | \ 191 FTIM1_NAND_TRR(0xe) | \ 192 FTIM1_NAND_TRP(0x18)) 193#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 194 FTIM2_NAND_TREH(0xa) | \ 195 FTIM2_NAND_TWHRE(0x1e)) 196#define CONFIG_SYS_NAND_FTIM3 0x0 197 198#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 199#define CONFIG_SYS_MAX_NAND_DEVICE 1 200#define CONFIG_MTD_NAND_VERIFY_WRITE 201 202#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 203#endif 204 205#ifdef CONFIG_NAND_BOOT 206#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 207#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 208#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 209#endif 210 211#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 212#define CONFIG_QIXIS_I2C_ACCESS 213#define CONFIG_SYS_I2C_EARLY_INIT 214#endif 215 216/* 217 * QIXIS Definitions 218 */ 219#define CONFIG_FSL_QIXIS 220 221#ifdef CONFIG_FSL_QIXIS 222#define QIXIS_BASE 0x7fb00000 223#define QIXIS_BASE_PHYS QIXIS_BASE 224#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 225#define QIXIS_LBMAP_SWITCH 6 226#define QIXIS_LBMAP_MASK 0x0f 227#define QIXIS_LBMAP_SHIFT 0 228#define QIXIS_LBMAP_DFLTBANK 0x00 229#define QIXIS_LBMAP_ALTBANK 0x04 230#define QIXIS_LBMAP_NAND 0x09 231#define QIXIS_LBMAP_SD 0x00 232#define QIXIS_LBMAP_SD_QSPI 0xff 233#define QIXIS_LBMAP_QSPI 0xff 234#define QIXIS_RCW_SRC_NAND 0x106 235#define QIXIS_RCW_SRC_SD 0x040 236#define QIXIS_RCW_SRC_QSPI 0x045 237#define QIXIS_RST_CTL_RESET 0x41 238#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 239#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 240#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 241 242#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 243#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 244 CSPR_PORT_SIZE_8 | \ 245 CSPR_MSEL_GPCM | \ 246 CSPR_V) 247#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 248#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 249 CSOR_NOR_NOR_MODE_AVD_NOR | \ 250 CSOR_NOR_TRHZ_80) 251 252/* 253 * QIXIS Timing parameters for IFC GPCM 254 */ 255#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 256 FTIM0_GPCM_TEADC(0x20) | \ 257 FTIM0_GPCM_TEAHC(0x10)) 258#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 259 FTIM1_GPCM_TRAD(0x1f)) 260#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 261 FTIM2_GPCM_TCH(0x8) | \ 262 FTIM2_GPCM_TWP(0xf0)) 263#define CONFIG_SYS_FPGA_FTIM3 0x0 264#endif 265 266#ifdef CONFIG_NAND_BOOT 267#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 268#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 269#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 270#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 271#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 272#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 273#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 274#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 275#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 276#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 277#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 278#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 279#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 280#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 281#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 282#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 283#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 284#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 285#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 286#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 287#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 288#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 289#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 290#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 291#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 292#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 293#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 294#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 295#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 296#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 297#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 298#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 299#else 300#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 301#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 302#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 303#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 304#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 305#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 306#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 307#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 308#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 309#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 310#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 311#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 312#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 313#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 314#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 315#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 316#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 317#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 318#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 319#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 320#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 321#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 322#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 323#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 324#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 325#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 326#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 327#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 328#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 329#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 330#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 331#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 332#endif 333 334/* 335 * I2C bus multiplexer 336 */ 337#define I2C_MUX_PCA_ADDR_PRI 0x77 338#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 339#define I2C_RETIMER_ADDR 0x18 340#define I2C_MUX_CH_DEFAULT 0x8 341#define I2C_MUX_CH_CH7301 0xC 342#define I2C_MUX_CH5 0xD 343#define I2C_MUX_CH7 0xF 344 345#define I2C_MUX_CH_VOL_MONITOR 0xa 346 347/* Voltage monitor on channel 2*/ 348#define I2C_VOL_MONITOR_ADDR 0x40 349#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 350#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 351#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 352 353#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 354#ifndef CONFIG_SPL_BUILD 355#define CONFIG_VID 356#endif 357#define CONFIG_VOL_MONITOR_IR36021_SET 358#define CONFIG_VOL_MONITOR_INA220 359/* The lowest and highest voltage allowed for LS1043AQDS */ 360#define VDD_MV_MIN 819 361#define VDD_MV_MAX 1212 362 363/* QSPI device */ 364#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 365#define CONFIG_FSL_QSPI 366#ifdef CONFIG_FSL_QSPI 367#define CONFIG_SPI_FLASH_SPANSION 368#define FSL_QSPI_FLASH_SIZE (1 << 24) 369#define FSL_QSPI_FLASH_NUM 2 370#endif 371#endif 372 373/* 374 * Miscellaneous configurable options 375 */ 376#define CONFIG_MISC_INIT_R 377#define CONFIG_SYS_LONGHELP /* undef to save memory */ 378#define CONFIG_AUTO_COMPLETE 379 380#define CONFIG_SYS_MEMTEST_START 0x80000000 381#define CONFIG_SYS_MEMTEST_END 0x9fffffff 382 383#define CONFIG_SYS_HZ 1000 384 385#define CONFIG_SYS_INIT_SP_OFFSET \ 386 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 387 388#ifdef CONFIG_SPL_BUILD 389#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 390#else 391#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 392#endif 393 394/* 395 * Environment 396 */ 397#define CONFIG_ENV_OVERWRITE 398 399#ifdef CONFIG_NAND_BOOT 400#define CONFIG_ENV_SIZE 0x2000 401#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 402#elif defined(CONFIG_SD_BOOT) 403#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 404#define CONFIG_SYS_MMC_ENV_DEV 0 405#define CONFIG_ENV_SIZE 0x2000 406#elif defined(CONFIG_QSPI_BOOT) 407#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 408#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 409#define CONFIG_ENV_SECT_SIZE 0x10000 410#else 411#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 412#define CONFIG_ENV_SECT_SIZE 0x20000 413#define CONFIG_ENV_SIZE 0x20000 414#endif 415 416#define CONFIG_CMDLINE_TAG 417 418#include <asm/fsl_secure_boot.h> 419 420#endif /* __LS1043AQDS_H__ */ 421