1/* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __LS1088A_QDS_H 8#define __LS1088A_QDS_H 9 10#include "ls1088a_common.h" 11 12 13#define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 16#ifndef __ASSEMBLY__ 17unsigned long get_board_sys_clk(void); 18unsigned long get_board_ddr_clk(void); 19#endif 20 21 22#if defined(CONFIG_QSPI_BOOT) 23#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 24#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 25#define CONFIG_ENV_SECT_SIZE 0x40000 26#else 27#define CONFIG_ENV_IS_IN_FLASH 28#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 29#define CONFIG_ENV_SECT_SIZE 0x20000 30#define CONFIG_ENV_SIZE 0x20000 31#endif 32 33#if defined(CONFIG_QSPI_BOOT) 34#define CONFIG_QIXIS_I2C_ACCESS 35#define SYS_NO_FLASH 36 37#define CONFIG_SYS_CLK_FREQ 100000000 38#define CONFIG_DDR_CLK_FREQ 100000000 39#else 40#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42#endif 43 44#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 45#define COUNTER_FREQUENCY 25000000 /* 25MHz */ 46 47#define CONFIG_DIMM_SLOTS_PER_CTLR 1 48 49#define CONFIG_DDR_SPD 50#define CONFIG_DDR_ECC 51#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 52#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 53#define SPD_EEPROM_ADDRESS 0x51 54#define CONFIG_SYS_SPD_BUS_NUM 0 55 56 57/* 58 * IFC Definitions 59 */ 60#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 61#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 62#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 63#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 64 65#define CONFIG_SYS_NOR0_CSPR \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 67 CSPR_PORT_SIZE_16 | \ 68 CSPR_MSEL_NOR | \ 69 CSPR_V) 70#define CONFIG_SYS_NOR0_CSPR_EARLY \ 71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 72 CSPR_PORT_SIZE_16 | \ 73 CSPR_MSEL_NOR | \ 74 CSPR_V) 75#define CONFIG_SYS_NOR1_CSPR \ 76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 77 CSPR_PORT_SIZE_16 | \ 78 CSPR_MSEL_NOR | \ 79 CSPR_V) 80#define CONFIG_SYS_NOR1_CSPR_EARLY \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 86#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 87 FTIM0_NOR_TEADC(0x5) | \ 88 FTIM0_NOR_TEAHC(0x5)) 89#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 90 FTIM1_NOR_TRAD_NOR(0x1a) |\ 91 FTIM1_NOR_TSEQRAD_NOR(0x13)) 92#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 93 FTIM2_NOR_TCH(0x4) | \ 94 FTIM2_NOR_TWPH(0x0E) | \ 95 FTIM2_NOR_TWP(0x1c)) 96#define CONFIG_SYS_NOR_FTIM3 0x04000000 97#define CONFIG_SYS_IFC_CCR 0x01000000 98 99#ifndef SYS_NO_FLASH 100#define CONFIG_FLASH_CFI_DRIVER 101#define CONFIG_SYS_FLASH_CFI 102#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 103#define CONFIG_SYS_FLASH_QUIET_TEST 104#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 105 106#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 107#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 108#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 109#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 110 111#define CONFIG_SYS_FLASH_EMPTY_INFO 112#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 113 CONFIG_SYS_FLASH_BASE + 0x40000000} 114#endif 115#endif 116 117#define CONFIG_NAND_FSL_IFC 118#define CONFIG_SYS_NAND_MAX_ECCPOS 256 119#define CONFIG_SYS_NAND_MAX_OOBFREE 2 120 121#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 122#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 123 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 124 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 125 | CSPR_V) 126#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 127 128#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 129 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 130 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 131 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 132 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 133 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 134 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 135 136#define CONFIG_SYS_NAND_ONFI_DETECTION 137 138/* ONFI NAND Flash mode0 Timing Params */ 139#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 140 FTIM0_NAND_TWP(0x18) | \ 141 FTIM0_NAND_TWCHT(0x07) | \ 142 FTIM0_NAND_TWH(0x0a)) 143#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 144 FTIM1_NAND_TWBE(0x39) | \ 145 FTIM1_NAND_TRR(0x0e) | \ 146 FTIM1_NAND_TRP(0x18)) 147#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 148 FTIM2_NAND_TREH(0x0a) | \ 149 FTIM2_NAND_TWHRE(0x1e)) 150#define CONFIG_SYS_NAND_FTIM3 0x0 151 152#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 153#define CONFIG_SYS_MAX_NAND_DEVICE 1 154#define CONFIG_MTD_NAND_VERIFY_WRITE 155#define CONFIG_CMD_NAND 156 157#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 158 159#define CONFIG_FSL_QIXIS 160#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 161#define QIXIS_LBMAP_SWITCH 6 162#define QIXIS_QMAP_MASK 0xe0 163#define QIXIS_QMAP_SHIFT 5 164#define QIXIS_LBMAP_MASK 0x0f 165#define QIXIS_LBMAP_SHIFT 0 166#define QIXIS_LBMAP_DFLTBANK 0x0e 167#define QIXIS_LBMAP_ALTBANK 0x2e 168#define QIXIS_LBMAP_SD 0x00 169#define QIXIS_LBMAP_SD_QSPI 0x0e 170#define QIXIS_LBMAP_QSPI 0x0e 171#define QIXIS_RCW_SRC_SD 0x40 172#define QIXIS_RCW_SRC_QSPI 0x62 173#define QIXIS_RST_CTL_RESET 0x41 174#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 175#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 176#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 177#define QIXIS_RST_FORCE_MEM 0x01 178#define QIXIS_STAT_PRES1 0xb 179#define QIXIS_SDID_MASK 0x07 180#define QIXIS_ESDHC_NO_ADAPTER 0x7 181 182#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 183#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 184 | CSPR_PORT_SIZE_8 \ 185 | CSPR_MSEL_GPCM \ 186 | CSPR_V) 187#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 188 | CSPR_PORT_SIZE_8 \ 189 | CSPR_MSEL_GPCM \ 190 | CSPR_V) 191 192#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 193#if defined(CONFIG_QSPI_BOOT) 194#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 195#else 196#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 197#endif 198/* QIXIS Timing parameters*/ 199#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 200 FTIM0_GPCM_TEADC(0x0e) | \ 201 FTIM0_GPCM_TEAHC(0x0e)) 202#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 203 FTIM1_GPCM_TRAD(0x3f)) 204#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 205 FTIM2_GPCM_TCH(0xf) | \ 206 FTIM2_GPCM_TWP(0x3E)) 207#define SYS_FPGA_CS_FTIM3 0x0 208 209#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 210#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 211#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 212#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 213#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 214#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 215#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 216#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 217#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 218#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 219#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 220#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 221#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 222#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 223#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 224#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 225#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 226#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 227#else 228#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 229#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 230#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 231#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 232#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 233#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 234#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 235#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 236#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 237#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 238#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 239#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 240#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 241#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 242#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 243#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 244#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 245#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 246#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 247#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 248#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 249#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 250#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 251#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 252#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 253#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 254#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 255#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 256#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 257#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL 258#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 259#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 260#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 261#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 262#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 263#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 264#endif 265 266#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 267 268/* 269 * I2C bus multiplexer 270 */ 271#define I2C_MUX_PCA_ADDR_PRI 0x77 272#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 273#define I2C_RETIMER_ADDR 0x18 274#define I2C_RETIMER_ADDR2 0x19 275#define I2C_MUX_CH_DEFAULT 0x8 276#define I2C_MUX_CH5 0xD 277 278/* 279* RTC configuration 280*/ 281#define RTC 282#define CONFIG_RTC_PCF8563 1 283#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 284#define CONFIG_CMD_DATE 285 286/* EEPROM */ 287#define CONFIG_ID_EEPROM 288#define CONFIG_SYS_I2C_EEPROM_NXID 289#define CONFIG_SYS_EEPROM_BUS_NUM 0 290#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 291#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 292#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 293#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 294 295/* QSPI device */ 296#if defined(CONFIG_QSPI_BOOT) 297#define CONFIG_FSL_QSPI 298#define CONFIG_SPI_FLASH_SPANSION 299#define FSL_QSPI_FLASH_SIZE (1 << 26) 300#define FSL_QSPI_FLASH_NUM 2 301 302#endif 303 304#ifdef CONFIG_FSL_DSPI 305#define CONFIG_SPI_FLASH_STMICRO 306#define CONFIG_SPI_FLASH_SST 307#define CONFIG_SPI_FLASH_EON 308#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 309#define CONFIG_SF_DEFAULT_BUS 1 310#define CONFIG_SF_DEFAULT_CS 0 311#endif 312#endif 313 314#define CONFIG_CMD_MEMINFO 315#define CONFIG_CMD_MEMTEST 316#define CONFIG_SYS_MEMTEST_START 0x80000000 317#define CONFIG_SYS_MEMTEST_END 0x9fffffff 318 319#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 320 321#define CONFIG_FSL_MEMAC 322 323/* MMC */ 324#define CONFIG_FSL_ESDHC 325#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 326#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 327 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 328 329/* Initial environment variables */ 330#if defined(CONFIG_QSPI_BOOT) 331#undef CONFIG_EXTRA_ENV_SETTINGS 332#define CONFIG_EXTRA_ENV_SETTINGS \ 333 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 334 "loadaddr=0x90100000\0" \ 335 "kernel_addr=0x100000\0" \ 336 "ramdisk_addr=0x800000\0" \ 337 "ramdisk_size=0x2000000\0" \ 338 "fdt_high=0xa0000000\0" \ 339 "initrd_high=0xffffffffffffffff\0" \ 340 "kernel_start=0x1000000\0" \ 341 "kernel_load=0xa0000000\0" \ 342 "kernel_size=0x2800000\0" \ 343 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 344 "sf read 0x80100000 0xE00000 0x100000;" \ 345 "fsl_mc start mc 0x80000000 0x80100000\0" \ 346 "mcmemsize=0x70000000 \0" 347#else /* NOR BOOT */ 348#undef CONFIG_EXTRA_ENV_SETTINGS 349#define CONFIG_EXTRA_ENV_SETTINGS \ 350 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 351 "loadaddr=0x90100000\0" \ 352 "kernel_addr=0x100000\0" \ 353 "ramdisk_addr=0x800000\0" \ 354 "ramdisk_size=0x2000000\0" \ 355 "fdt_high=0xa0000000\0" \ 356 "initrd_high=0xffffffffffffffff\0" \ 357 "kernel_start=0x1000000\0" \ 358 "kernel_load=0xa0000000\0" \ 359 "kernel_size=0x2800000\0" \ 360 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 361 "mcmemsize=0x70000000 \0" 362#endif 363 364#ifdef CONFIG_FSL_MC_ENET 365#define CONFIG_FSL_MEMAC 366#define CONFIG_PHYLIB 367#define CONFIG_PHYLIB_10G 368#define CONFIG_PHY_VITESSE 369#define CONFIG_PHY_REALTEK 370#define CONFIG_PHY_TERANETICS 371#define RGMII_PHY1_ADDR 0x1 372#define RGMII_PHY2_ADDR 0x2 373#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 374#define SGMII_CARD_PORT2_PHY_ADDR 0x1d 375#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 376#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 377 378#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 379#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 380#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 381#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 382#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 383#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 384#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 385#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 386#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 387#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 388#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 389#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 390#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 391#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 392#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 393#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 394 395#define CONFIG_MII /* MII PHY management */ 396#define CONFIG_ETHPRIME "DPMAC1@xgmii" 397#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 398 399#endif 400 401#undef CONFIG_CMDLINE_EDITING 402#include <config_distro_defaults.h> 403#define BOOT_TARGET_DEVICES(func) \ 404 func(USB, usb, 0) \ 405 func(MMC, mmc, 0) \ 406 func(SCSI, scsi, 0) \ 407 func(DHCP, dhcp, na) 408#include <config_distro_bootcmd.h> 409 410#include <asm/fsl_secure_boot.h> 411 412#endif /* __LS1088A_QDS_H */ 413