1/* 2 * (C) Copyright 2010 3 * Ilko Iliev <iliev@ronetix.at> 4 * Asen Dimov <dimov@ronetix.at> 5 * Ronetix GmbH <www.ronetix.at> 6 * 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * Configuation settings for the PM9G45 board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#ifndef __CONFIG_H 17#define __CONFIG_H 18 19/* 20 * SoC must be defined first, before hardware.h is included. 21 * In this case SoC is defined in boards.cfg. 22 */ 23#include <asm/hardware.h> 24 25#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ 26#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" 27 28#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 29 30/* ARM asynchronous clock */ 31#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 32#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 33#define CONFIG_SYS_TEXT_BASE 0x73f00000 34 35#define CONFIG_ARCH_CPU_INIT 36 37#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 38#define CONFIG_SETUP_MEMORY_TAGS 1 39#define CONFIG_INITRD_TAG 1 40 41#define CONFIG_SKIP_LOWLEVEL_INIT 42 43/* 44 * Hardware drivers 45 */ 46#define CONFIG_AT91_GPIO 1 47#define CONFIG_ATMEL_USART 1 48#define CONFIG_USART_BASE ATMEL_BASE_DBGU 49#define CONFIG_USART_ID ATMEL_ID_SYS 50 51#define CONFIG_SYS_USE_NANDFLASH 1 52 53/* LED */ 54#define CONFIG_AT91_LED 55#define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ 56#define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ 57 58 59/* 60 * BOOTP options 61 */ 62#define CONFIG_BOOTP_BOOTFILESIZE 1 63#define CONFIG_BOOTP_BOOTPATH 1 64#define CONFIG_BOOTP_GATEWAY 1 65#define CONFIG_BOOTP_HOSTNAME 1 66 67#define CONFIG_JFFS2_CMDLINE 1 68#define CONFIG_JFFS2_NAND 1 69#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 70#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 71#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 72 73/* SDRAM */ 74#define CONFIG_NR_DRAM_BANKS 1 75#define PHYS_SDRAM 0x70000000 76#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 77 78/* NAND flash */ 79#ifdef CONFIG_CMD_NAND 80#define CONFIG_NAND_ATMEL 81#define CONFIG_SYS_MAX_NAND_DEVICE 1 82#define CONFIG_SYS_NAND_BASE 0x40000000 83#define CONFIG_SYS_NAND_DBW_8 1 84/* our ALE is AD21 */ 85#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 86/* our CLE is AD22 */ 87#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 88#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 89#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) 90 91#endif 92 93/* Ethernet */ 94#define CONFIG_MACB 1 95#define CONFIG_RMII 1 96#define CONFIG_NET_RETRY_COUNT 20 97#define CONFIG_RESET_PHY_R 1 98 99/* USB */ 100#define CONFIG_USB_ATMEL 101#define CONFIG_USB_ATMEL_CLK_SEL_UPLL 102#define CONFIG_USB_OHCI_NEW 1 103#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 104#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 105#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 106#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 107 108/* board specific(not enough SRAM) */ 109#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 110 111#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 112 113#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 114#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 115 116/* bootstrap + u-boot + env + linux in nandflash */ 117#define CONFIG_ENV_OFFSET 0x60000 118#define CONFIG_ENV_OFFSET_REDUND 0x80000 119#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 120#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 121 122#define CONFIG_SYS_LONGHELP 1 123#define CONFIG_CMDLINE_EDITING 1 124#define CONFIG_AUTO_COMPLETE 125 126/* 127 * Size of malloc() pool 128 */ 129#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 130 0x1000) 131 132#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 133#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 134 GENERATED_GBL_DATA_SIZE) 135 136#endif 137