1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 9 10#define CCM_CCOSR 0x020c4060 11#define CCM_CCGR0 0x020C4068 12#define CCM_CCGR1 0x020C406c 13#define CCM_CCGR2 0x020C4070 14#define CCM_CCGR3 0x020C4074 15#define CCM_CCGR4 0x020C4078 16#define CCM_CCGR5 0x020C407c 17#define CCM_CCGR6 0x020C4080 18 19#define PMU_MISC2 0x020C8170 20 21#ifndef __ASSEMBLY__ 22struct mxc_ccm_reg { 23 u32 ccr; /* 0x0000 */ 24 u32 ccdr; 25 u32 csr; 26 u32 ccsr; 27 u32 cacrr; /* 0x0010*/ 28 u32 cbcdr; 29 u32 cbcmr; 30 u32 cscmr1; 31 u32 cscmr2; /* 0x0020 */ 32 u32 cscdr1; 33 u32 cs1cdr; 34 u32 cs2cdr; 35 u32 cdcdr; /* 0x0030 */ 36 u32 chsccdr; 37 u32 cscdr2; 38 u32 cscdr3; 39 u32 cscdr4; /* 0x0040 */ 40 u32 resv0; 41 u32 cdhipr; 42 u32 cdcr; 43 u32 ctor; /* 0x0050 */ 44 u32 clpcr; 45 u32 cisr; 46 u32 cimr; 47 u32 ccosr; /* 0x0060 */ 48 u32 cgpr; 49 u32 CCGR0; 50 u32 CCGR1; 51 u32 CCGR2; /* 0x0070 */ 52 u32 CCGR3; 53 u32 CCGR4; 54 u32 CCGR5; 55 u32 CCGR6; /* 0x0080 */ 56 u32 CCGR7; 57 u32 cmeor; 58 u32 resv[0xfdd]; 59 u32 analog_pll_sys; /* 0x4000 */ 60 u32 analog_pll_sys_set; 61 u32 analog_pll_sys_clr; 62 u32 analog_pll_sys_tog; 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 64 u32 analog_usb1_pll_480_ctrl_set; 65 u32 analog_usb1_pll_480_ctrl_clr; 66 u32 analog_usb1_pll_480_ctrl_tog; 67 u32 analog_reserved0[4]; 68 u32 analog_pll_528; /* 0x4030 */ 69 u32 analog_pll_528_set; 70 u32 analog_pll_528_clr; 71 u32 analog_pll_528_tog; 72 u32 analog_pll_528_ss; /* 0x4040 */ 73 u32 analog_reserved1[3]; 74 u32 analog_pll_528_num; /* 0x4050 */ 75 u32 analog_reserved2[3]; 76 u32 analog_pll_528_denom; /* 0x4060 */ 77 u32 analog_reserved3[3]; 78 u32 analog_pll_audio; /* 0x4070 */ 79 u32 analog_pll_audio_set; 80 u32 analog_pll_audio_clr; 81 u32 analog_pll_audio_tog; 82 u32 analog_pll_audio_num; /* 0x4080*/ 83 u32 analog_reserved4[3]; 84 u32 analog_pll_audio_denom; /* 0x4090 */ 85 u32 analog_reserved5[3]; 86 u32 analog_pll_video; /* 0x40a0 */ 87 u32 analog_pll_video_set; 88 u32 analog_pll_video_clr; 89 u32 analog_pll_video_tog; 90 u32 analog_pll_video_num; /* 0x40b0 */ 91 u32 analog_reserved6[3]; 92 u32 analog_pll_video_denom; /* 0x40c0 */ 93 u32 analog_reserved7[7]; 94 u32 analog_pll_enet; /* 0x40e0 */ 95 u32 analog_pll_enet_set; 96 u32 analog_pll_enet_clr; 97 u32 analog_pll_enet_tog; 98 u32 analog_pfd_480; /* 0x40f0 */ 99 u32 analog_pfd_480_set; 100 u32 analog_pfd_480_clr; 101 u32 analog_pfd_480_tog; 102 u32 analog_pfd_528; /* 0x4100 */ 103 u32 analog_pfd_528_set; 104 u32 analog_pfd_528_clr; 105 u32 analog_pfd_528_tog; 106 /* PMU Memory Map/Register Definition */ 107 u32 pmu_reg_1p1; 108 u32 pmu_reg_1p1_set; 109 u32 pmu_reg_1p1_clr; 110 u32 pmu_reg_1p1_tog; 111 u32 pmu_reg_3p0; 112 u32 pmu_reg_3p0_set; 113 u32 pmu_reg_3p0_clr; 114 u32 pmu_reg_3p0_tog; 115 u32 pmu_reg_2p5; 116 u32 pmu_reg_2p5_set; 117 u32 pmu_reg_2p5_clr; 118 u32 pmu_reg_2p5_tog; 119 u32 pmu_reg_core; 120 u32 pmu_reg_core_set; 121 u32 pmu_reg_core_clr; 122 u32 pmu_reg_core_tog; 123 u32 pmu_misc0; 124 u32 pmu_misc0_set; 125 u32 pmu_misc0_clr; 126 u32 pmu_misc0_tog; 127 u32 pmu_misc1; 128 u32 pmu_misc1_set; 129 u32 pmu_misc1_clr; 130 u32 pmu_misc1_tog; 131 u32 pmu_misc2; 132 u32 pmu_misc2_set; 133 u32 pmu_misc2_clr; 134 u32 pmu_misc2_tog; 135 /* TEMPMON Memory Map/Register Definition */ 136 u32 tempsense0; 137 u32 tempsense0_set; 138 u32 tempsense0_clr; 139 u32 tempsense0_tog; 140 u32 tempsense1; 141 u32 tempsense1_set; 142 u32 tempsense1_clr; 143 u32 tempsense1_tog; 144 /* USB Analog Memory Map/Register Definition */ 145 u32 usb1_vbus_detect; 146 u32 usb1_vbus_detect_set; 147 u32 usb1_vbus_detect_clr; 148 u32 usb1_vbus_detect_tog; 149 u32 usb1_chrg_detect; 150 u32 usb1_chrg_detect_set; 151 u32 usb1_chrg_detect_clr; 152 u32 usb1_chrg_detect_tog; 153 u32 usb1_vbus_det_stat; 154 u32 usb1_vbus_det_stat_set; 155 u32 usb1_vbus_det_stat_clr; 156 u32 usb1_vbus_det_stat_tog; 157 u32 usb1_chrg_det_stat; 158 u32 usb1_chrg_det_stat_set; 159 u32 usb1_chrg_det_stat_clr; 160 u32 usb1_chrg_det_stat_tog; 161 u32 usb1_loopback; 162 u32 usb1_loopback_set; 163 u32 usb1_loopback_clr; 164 u32 usb1_loopback_tog; 165 u32 usb1_misc; 166 u32 usb1_misc_set; 167 u32 usb1_misc_clr; 168 u32 usb1_misc_tog; 169 u32 usb2_vbus_detect; 170 u32 usb2_vbus_detect_set; 171 u32 usb2_vbus_detect_clr; 172 u32 usb2_vbus_detect_tog; 173 u32 usb2_chrg_detect; 174 u32 usb2_chrg_detect_set; 175 u32 usb2_chrg_detect_clr; 176 u32 usb2_chrg_detect_tog; 177 u32 usb2_vbus_det_stat; 178 u32 usb2_vbus_det_stat_set; 179 u32 usb2_vbus_det_stat_clr; 180 u32 usb2_vbus_det_stat_tog; 181 u32 usb2_chrg_det_stat; 182 u32 usb2_chrg_det_stat_set; 183 u32 usb2_chrg_det_stat_clr; 184 u32 usb2_chrg_det_stat_tog; 185 u32 usb2_loopback; 186 u32 usb2_loopback_set; 187 u32 usb2_loopback_clr; 188 u32 usb2_loopback_tog; 189 u32 usb2_misc; 190 u32 usb2_misc_set; 191 u32 usb2_misc_clr; 192 u32 usb2_misc_tog; 193 u32 digprog; 194 u32 reserved1[7]; 195 /* For i.MX 6SoloLite */ 196 u32 digprog_sololite; 197}; 198#endif 199 200/* Define the bits in register CCR */ 201#define MXC_CCM_CCR_RBC_EN (1 << 27) 202#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 203#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 204/* CCR_WB does not exist on i.MX6SX/UL */ 205#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 206#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 207#define MXC_CCM_CCR_COSC_EN (1 << 12) 208#ifdef CONFIG_MX6SX 209#define MXC_CCM_CCR_OSCNT_MASK 0x7F 210#else 211#define MXC_CCM_CCR_OSCNT_MASK 0xFF 212#endif 213#define MXC_CCM_CCR_OSCNT_OFFSET 0 214 215/* Define the bits in register CCDR */ 216#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 217#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 218/* Exists on i.MX6QP */ 219#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) 220 221/* Define the bits in register CSR */ 222#define MXC_CCM_CSR_COSC_READY (1 << 5) 223#define MXC_CCM_CSR_REF_EN_B (1 << 0) 224 225/* Define the bits in register CCSR */ 226#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 227#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 228#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 229#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 230#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 231#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 232#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 233#define MXC_CCM_CCSR_STEP_SEL (1 << 8) 234#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 235#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 236#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 237 238/* Define the bits in register CACRR */ 239#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 240#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 241 242/* Define the bits in register CBCDR */ 243#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 244#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 245#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) 246#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 247/* MMDC_CH0 not exists on i.MX6SX */ 248#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 249#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 250#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 251#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 252#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 253#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 254#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 255#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 256#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 257#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 258#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 259#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 260#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 261#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 262 263/* Define the bits in register CBCMR */ 264#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 265#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 266#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 267#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 268/* LCDIF on i.MX6SX/UL */ 269#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) 270#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 271#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 272#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 273#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 274#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 275#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) 276#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 277#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 278#ifndef CONFIG_MX6SX 279#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 280#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 281#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 282#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 283#endif 284#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 285#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 286#ifndef CONFIG_MX6SX 287#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 288#endif 289#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 290#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 291#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 292#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 293#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 294/* Exists on i.MX6QP */ 295#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) 296 297/* Define the bits in register CSCMR1 */ 298#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 299#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 300/* QSPI1 exist on i.MX6SX/UL */ 301#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 302#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 303#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 304#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 305#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 306#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 307/* LCFIF2_PODF on i.MX6SX */ 308#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) 309#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 310/* LCDIF_PIX_PODF on i.MX6SL */ 311#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20) 312#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20 313/* ACLK_EMI on i.MX6DQ/SDL/DQP */ 314#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 315#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 316/* CSCMR1_GPMI/BCH exist on i.MX6UL */ 317#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) 318#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) 319#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 320#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 321#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 322#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 323#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 324#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 325#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 326#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 327#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 328#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 329/* QSPI1 exist on i.MX6SX/UL */ 330#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 331#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 332/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ 333#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 334#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 335 336#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 337 338/* Define the bits in register CSCMR2 */ 339#ifdef CONFIG_MX6SX 340#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 341#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 342#endif 343#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 344#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 345#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 346#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 347/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ 348#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 349#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 350 351#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 352#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 353 354/* Define the bits in register CSCDR1 */ 355#ifndef CONFIG_MX6SX 356#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 357#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 358#endif 359/* CSCDR1_GPMI/BCH exist on i.MX6UL */ 360#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) 361#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 362#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) 363#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 364 365#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 366#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 367#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 368#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 369#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 370#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 371#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 372#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 373#ifndef CONFIG_MX6SX 374#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 375#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 376#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 377#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 378#endif 379#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 380#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 381/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ 382#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 383 384/* Define the bits in register CS1CDR */ 385/* MX6UL, !MX6ULL */ 386#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) 387#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 388#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) 389#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 390#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) 391#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 392#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F 393#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 394 395#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 396#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 397#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 398#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 399#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 400#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 401#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 402#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 403#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 404#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 405#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 406#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 407 408/* Define the bits in register CS2CDR */ 409/* QSPI2 on i.MX6SX */ 410#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 411#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 412#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 413#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 414#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 415#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 416#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 417#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 418#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 419 420#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 421#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 422#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 423#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 424#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 425#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 426 427#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) 428#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 429#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) 430#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) 431#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 432#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) 433 434#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ 435 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 436 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ 437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) 438#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ 439 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 440 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ 441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) 442#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ 443 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 444 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ 445 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) 446 447#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 448#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 449#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 450#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 451#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 452#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 453#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 454#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 455 456/* Define the bits in register CDCDR */ 457#ifndef CONFIG_MX6SX 458#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 459#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 460#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 461#endif 462#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 463#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 464#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 465#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 466#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 467#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 468#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 469#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 470#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 471#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 472#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 473#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 474 475/* Define the bits in register CHSCCDR */ 476/* i.MX6SX */ 477#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 478#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 479#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 480#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 481#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 482#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 483#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 484#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 485#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 486#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 487#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 488#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 489 490#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 491#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 492#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 493#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 494#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 495#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 496#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 497#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 498#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 499#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 500#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 501#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 502 503/* i.MX6ULL */ 504#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) 505#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 506#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) 507#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 508#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) 509#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 510 511#define CHSCCDR_CLK_SEL_LDB_DI0 3 512#define CHSCCDR_PODF_DIVIDE_BY_3 2 513#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 514 515/* Define the bits in register CSCDR2 */ 516#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 517#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 518/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ 519#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) 520/* LCDIF1 on i.MX6SX/UL */ 521#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) 522#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 523#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) 524#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 525#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) 526#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 527/* LCDIF2 on i.MX6SX */ 528#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) 529#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 530#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) 531#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 532#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) 533#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 534 535/*LCD on i.MX6SL */ 536#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6) 537#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6 538#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3) 539#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3 540 541/* All IPU2_DI1 are LCDIF1 on MX6SX */ 542#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 543#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 544#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 545#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 546#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 547#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 548/* All IPU2_DI0 are LCDIF2 on MX6SX */ 549#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 550#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 551#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 552#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 553#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 554#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 555 556/* Define the bits in register CSCDR3 */ 557#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 558#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 559#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 560#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 561#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 562#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 563#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 564#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 565 566/* For i.MX6SL */ 567#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16) 568#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 569#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) 570#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 571 572/* Define the bits in register CDHIPR */ 573#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 574#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 575#ifndef CONFIG_MX6SX 576#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 577#endif 578#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 579#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 580#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 581#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 582 583/* Define the bits in register CLPCR */ 584#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 585#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 586#ifndef CONFIG_MX6SX 587#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 588#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 589#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 590#endif 591#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 592#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 593#ifndef CONFIG_MX6SX 594#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 595#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 596#endif 597#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 598#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 599#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 600#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 601#define MXC_CCM_CLPCR_VSTBY (1 << 8) 602#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 603#define MXC_CCM_CLPCR_SBYOS (1 << 6) 604#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 605#ifndef CONFIG_MX6SX 606#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 607#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 608#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 609#endif 610#define MXC_CCM_CLPCR_LPM_MASK 0x3 611#define MXC_CCM_CLPCR_LPM_OFFSET 0 612 613/* Define the bits in register CISR */ 614#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 615#ifndef CONFIG_MX6SX 616#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 617#endif 618#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 619#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 620#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 621#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 622#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 623#define MXC_CCM_CISR_COSC_READY (1 << 6) 624#define MXC_CCM_CISR_LRF_PLL 1 625 626/* Define the bits in register CIMR */ 627#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 628#ifndef CONFIG_MX6SX 629#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 630#endif 631#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 632#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 633#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 634#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 635#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 636#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 637#define MXC_CCM_CIMR_MASK_LRF_PLL 1 638 639/* Define the bits in register CCOSR */ 640#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 641#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 642#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 643#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 644#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 645#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 646#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 647#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 648#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 649#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 650#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 651 652/* Define the bits in registers CGPR */ 653#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 654#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 655#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 656#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 657 658/* Define the bits in registers CCGRx */ 659#define MXC_CCM_CCGR_CG_MASK 3 660 661/* i.MX 6ULL */ 662#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 663#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) 664#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 665#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) 666 667#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 668#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 669#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 670#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 671#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 672#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 673#define MXC_CCM_CCGR0_ASRC_OFFSET 6 674#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 675#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 676#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 677#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 678#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 679#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 680#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 681#define MXC_CCM_CCGR0_CAN1_OFFSET 14 682#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 683#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 684#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 685#define MXC_CCM_CCGR0_CAN2_OFFSET 18 686#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 687#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 688#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 689#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 690#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 691#define MXC_CCM_CCGR0_DCIC1_OFFSET 24 692#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 693#define MXC_CCM_CCGR0_DCIC2_OFFSET 26 694#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 695#ifdef CONFIG_MX6SX 696#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 697#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 698#else 699#define MXC_CCM_CCGR0_DTCP_OFFSET 28 700#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 701#endif 702 703#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 704#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 705#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 706#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 707#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 708#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 709#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 710#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 711#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 712#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 713/* CCGR1_ENET does not exist on i.MX6SX/UL */ 714#define MXC_CCM_CCGR1_ENET_OFFSET 10 715#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) 716#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 717#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 718#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 719#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 720#define MXC_CCM_CCGR1_ESAIS_OFFSET 16 721#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 722#ifdef CONFIG_MX6SX 723#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 724#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 725#endif 726#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 727#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 728#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 729#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 730#ifndef CONFIG_MX6SX 731#define MXC_CCM_CCGR1_GPU2D_OFFSET 24 732#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 733#endif 734#define MXC_CCM_CCGR1_GPU3D_OFFSET 26 735#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 736#ifdef CONFIG_MX6SX 737#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 738#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 739#define MXC_CCM_CCGR1_CANFD_OFFSET 30 740#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 741#endif 742 743#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 744#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 745/* i.MX6SX/UL */ 746#define MXC_CCM_CCGR2_CSI_OFFSET 2 747#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 748 749#ifndef CONFIG_MX6SX 750#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 751#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 752#endif 753#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 754#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 755#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 756#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 757#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 758#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 759#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 760#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) 761#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 762#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 763#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 764#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 765#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 766#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 767#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 768#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 769#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 770#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 771#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 772#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 773/* i.MX6SX/UL LCD and PXP */ 774#define MXC_CCM_CCGR2_LCD_OFFSET 28 775#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 776#define MXC_CCM_CCGR2_PXP_OFFSET 30 777#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 778 779#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 780#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 781#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 782#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 783 784/* i.MX6ULL */ 785#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 786#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) 787#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 788#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) 789 790/* Exist on i.MX6SX */ 791#define MXC_CCM_CCGR3_M4_OFFSET 2 792#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 793/* i.MX6ULL */ 794#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 795#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) 796#define MXC_CCM_CCGR3_ENET_OFFSET 4 797#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 798#define MXC_CCM_CCGR3_QSPI_OFFSET 14 799#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 800 801/* i.MX6SL */ 802#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 803#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) 804#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 805#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) 806 807#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 808#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 809#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 810#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 811#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 812#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 813 814#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 815#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 816#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 817#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 818#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 819#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 820#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 821#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 822 823/* QSPI1 exists on i.MX6SX/UL */ 824#define MXC_CCM_CCGR3_QSPI1_OFFSET 14 825#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 826 827#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 828#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 829#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 830#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 831 832/* A7_CLKDIV/WDOG1 on i.MX6UL */ 833#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 834#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) 835#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 836#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) 837 838#define MXC_CCM_CCGR3_MLB_OFFSET 18 839#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 840#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 841#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 842#ifndef CONFIG_MX6SX 843#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 844#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 845#endif 846#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 847#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 848#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 849#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 850 851#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 852#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) 853#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 854#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) 855#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 856#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) 857/* AXI on i.MX6UL */ 858#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 859#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) 860#define MXC_CCM_CCGR3_OCRAM_OFFSET 28 861#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 862 863/* GPIO4 on i.MX6UL/ULL */ 864#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 865#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) 866 867#ifndef CONFIG_MX6SX 868#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 869#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 870#endif 871 872/* i.MX6ULL */ 873#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 874#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) 875 876#define MXC_CCM_CCGR4_PCIE_OFFSET 0 877#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 878/* QSPI2 on i.MX6SX */ 879#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 880#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 881#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 882#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 883#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 884#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 885#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 886#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 887#define MXC_CCM_CCGR4_PWM1_OFFSET 16 888#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 889#define MXC_CCM_CCGR4_PWM2_OFFSET 18 890#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 891#define MXC_CCM_CCGR4_PWM3_OFFSET 20 892#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 893#define MXC_CCM_CCGR4_PWM4_OFFSET 22 894#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 895#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 896#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 897#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 898#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 899#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 900#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 901#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 902#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 903 904#define MXC_CCM_CCGR5_ROM_OFFSET 0 905#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 906#ifndef CONFIG_MX6SX 907#define MXC_CCM_CCGR5_SATA_OFFSET 4 908#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 909#endif 910#define MXC_CCM_CCGR5_SDMA_OFFSET 6 911#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 912#define MXC_CCM_CCGR5_SPBA_OFFSET 12 913#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 914#define MXC_CCM_CCGR5_SPDIF_OFFSET 14 915#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 916#define MXC_CCM_CCGR5_SSI1_OFFSET 18 917#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 918#define MXC_CCM_CCGR5_SSI2_OFFSET 20 919#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 920#define MXC_CCM_CCGR5_SSI3_OFFSET 22 921#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 922#define MXC_CCM_CCGR5_UART_OFFSET 24 923#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 924#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 925#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 926#ifdef CONFIG_MX6SX 927#define MXC_CCM_CCGR5_SAI1_OFFSET 20 928#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 929#define MXC_CCM_CCGR5_SAI2_OFFSET 30 930#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 931#endif 932 933/* PRG_CLK0 exists on i.MX6QP */ 934#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) 935 936#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 937#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 938#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 939#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 940#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 941#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 942#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 943#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) 944#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 945#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) 946/* i.MX6ULL */ 947#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 948#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) 949/* GPMI/BCH on i.MX6UL */ 950#define MXC_CCM_CCGR6_BCH_OFFSET 6 951#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) 952#define MXC_CCM_CCGR6_GPMI_OFFSET 8 953#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) 954 955#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 956#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 957#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 958#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 959#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 960#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 961/* i.MX6ULL */ 962#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 963#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) 964/* The following *CCGR6* exist only i.MX6SX */ 965#define MXC_CCM_CCGR6_PWM8_OFFSET 16 966#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 967#define MXC_CCM_CCGR6_VADC_OFFSET 20 968#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 969#define MXC_CCM_CCGR6_GIS_OFFSET 22 970#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 971#define MXC_CCM_CCGR6_I2C4_OFFSET 24 972#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 973#define MXC_CCM_CCGR6_PWM5_OFFSET 26 974#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 975#define MXC_CCM_CCGR6_PWM6_OFFSET 28 976#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 977#define MXC_CCM_CCGR6_PWM7_OFFSET 30 978#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 979/* The two does not exist on i.MX6SX */ 980#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 981#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 982 983#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 984#define BP_ANADIG_PLL_SYS_RSVD0 20 985#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 986#define BF_ANADIG_PLL_SYS_RSVD0(v) \ 987 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 988#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 989#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 990#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 991#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 992#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 993#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 994#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 995 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 996#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 997#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 998#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 999#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 1000#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
1001#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 1002#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 1003#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 1004#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 1005#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 1006#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 1007#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 1008#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 1009#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 1010 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 1011 1012#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 1013#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 1014#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 1015#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 1016 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 1017#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 1018#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 1019#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 1020#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 1021 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 1022#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 1023#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 1024#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 1025#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 1026#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 1027#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 1028#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 1029#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 1030#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 1031#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 1032#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 1033#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 1034#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 1035#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 1036#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 1037#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 1038 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 1039#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 1040#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 1041#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 1042 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 1043 1044#define BM_ANADIG_PLL_528_LOCK 0x80000000 1045#define BP_ANADIG_PLL_528_RSVD1 19 1046#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 1047#define BF_ANADIG_PLL_528_RSVD1(v) \ 1048 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 1049#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 1050#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 1051#define BM_ANADIG_PLL_528_BYPASS 0x00010000 1052#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 1053#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 1054#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 1055 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 1056#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 1057#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 1058#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 1059#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 1060#define BM_ANADIG_PLL_528_ENABLE 0x00002000 1061#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 1062#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 1063#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 1064#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 1065#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 1066#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 1067#define BP_ANADIG_PLL_528_RSVD0 1 1068#define BM_ANADIG_PLL_528_RSVD0 0x0000007E 1069#define BF_ANADIG_PLL_528_RSVD0(v) \ 1070 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 1071#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 1072 1073#define BP_ANADIG_PLL_528_SS_STOP 16 1074#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 1075#define BF_ANADIG_PLL_528_SS_STOP(v) \ 1076 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 1077#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 1078#define BP_ANADIG_PLL_528_SS_STEP 0 1079#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 1080#define BF_ANADIG_PLL_528_SS_STEP(v) \ 1081 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 1082 1083#define BP_ANADIG_PLL_528_NUM_RSVD0 30 1084#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 1085#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 1086 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 1087#define BP_ANADIG_PLL_528_NUM_A 0 1088#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 1089#define BF_ANADIG_PLL_528_NUM_A(v) \ 1090 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 1091 1092#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 1093#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 1094#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 1095 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 1096#define BP_ANADIG_PLL_528_DENOM_B 0 1097#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 1098#define BF_ANADIG_PLL_528_DENOM_B(v) \ 1099 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 1100 1101#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 1102#define BP_ANADIG_PLL_AUDIO_RSVD0 22 1103#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 1104#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 1105 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 1106#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 1107#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 1108#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 1109#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 1110 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 1111#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 1112#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 1113#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 1114#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 1115#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 1116#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 1117 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 1118#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 1119#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 1120#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 1121#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 1122#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 1123#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 1124#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 1125#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 1126#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 1127#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 1128#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 1129#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 1130#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 1131#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 1132 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 1133 1134#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 1135#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 1136#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 1137 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 1138#define BP_ANADIG_PLL_AUDIO_NUM_A 0 1139#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 1140#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 1141 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 1142 1143#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 1144#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 1145#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 1146 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 1147#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 1148#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 1149#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 1150 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 1151 1152#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 1153#define BP_ANADIG_PLL_VIDEO_RSVD0 22 1154#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 1155#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 1156 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 1157#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 1158#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 1159#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 1160#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 1161 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 1162#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 1163#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 1164#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 1165#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 1166#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 1167#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 1168 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 1169#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 1170#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 1171#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 1172#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 1173#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 1174#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 1175#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 1176#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 1177#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 1178#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 1179#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 1180#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 1181#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 1182#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 1183 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 1184 1185#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 1186#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 1187#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 1188 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 1189#define BP_ANADIG_PLL_VIDEO_NUM_A 0 1190#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 1191#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 1192 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 1193 1194#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 1195#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 1196#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 1197 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 1198#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 1199#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 1200#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 1201 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 1202 1203#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 1204#define BP_ANADIG_PLL_ENET_RSVD1 21 1205#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 1206#define BF_ANADIG_PLL_ENET_RSVD1(v) \ 1207 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 1208#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 1209#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 1210#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 1211#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 1212#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 1213#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 1214#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 1215#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 1216#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 1217 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 1218#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 1219#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 1220#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 1221#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1222#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1223#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1224#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1225#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1226#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1227#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1228#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1229#define BP_ANADIG_PLL_ENET_RSVD0 2 1230#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1231#define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1232 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1233#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1234#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1235#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1236 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1237 1238/* ENET2 for i.MX6SX/UL */ 1239#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 1240#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C 1241#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ 1242 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) 1243 1244#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1245#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1246#define BP_ANADIG_PFD_480_PFD3_FRAC 24 1247#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1248#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1249 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1250#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1251#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1252#define BP_ANADIG_PFD_480_PFD2_FRAC 16 1253#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1254#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1255 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1256#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1257#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1258#define BP_ANADIG_PFD_480_PFD1_FRAC 8 1259#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1260#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1261 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1262#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1263#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1264#define BP_ANADIG_PFD_480_PFD0_FRAC 0 1265#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1266#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1267 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1268 1269#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1270#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1271#define BP_ANADIG_PFD_528_PFD3_FRAC 24 1272#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1273#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1274 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1275#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1276#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1277#define BP_ANADIG_PFD_528_PFD2_FRAC 16 1278#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1279#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1280 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1281#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1282#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1283#define BP_ANADIG_PFD_528_PFD1_FRAC 8 1284#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1285#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1286 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1287#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1288#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1289#define BP_ANADIG_PFD_528_PFD0_FRAC 0 1290#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1291#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1292 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1293 1294#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1295#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60 1296#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4 1297 1298#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) 1299#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 1300 1301#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) 1302#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 1303 1304#define PMU_MISC2_AUDIO_DIV(v) \ 1305 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ 1306 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ 1307 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ 1308 BP_PMU_MISC2_AUDIO_DIV_LSB)) 1309 1310#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1311