1/* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * 8 * Derived from OMAP3 work by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15#ifndef _OMAP4_H_ 16#define _OMAP4_H_ 17 18#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 19#include <asm/types.h> 20#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 21 22#include <linux/sizes.h> 23 24/* 25 * L4 Peripherals - L4 Wakeup and L4 Core now 26 */ 27#define OMAP44XX_L4_CORE_BASE 0x4A000000 28#define OMAP44XX_L4_WKUP_BASE 0x4A300000 29#define OMAP44XX_L4_PER_BASE 0x48000000 30 31#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 32#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 33#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 34#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 35 36/* CONTROL_ID_CODE */ 37#define CONTROL_ID_CODE 0x4A002204 38 39#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 40#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 41#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 42#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 43#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 44#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F 45#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F 46#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F 47 48/* UART */ 49#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 50#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 51#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 52 53/* General Purpose Timers */ 54#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 55#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 56#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 57 58/* Watchdog Timer2 - MPU watchdog */ 59#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 60 61/* 62 * Hardware Register Details 63 */ 64 65/* Watchdog Timer */ 66#define WD_UNLOCK1 0xAAAA 67#define WD_UNLOCK2 0x5555 68 69/* GP Timer */ 70#define TCLR_ST (0x1 << 0) 71#define TCLR_AR (0x1 << 1) 72#define TCLR_PRE (0x1 << 5) 73 74/* Control Module */ 75#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 76#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 77#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 78#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 79 80/* LPDDR2 IO regs */ 81#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 82#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 83#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 84#define LPDDR2IO_GR10_WD_MASK (3 << 17) 85#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F 86 87/* CONTROL_EFUSE_2 */ 88#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 89 90#define MMC1_PWRDNZ (1 << 26) 91#define MMC1_PBIASLITE_PWRDNZ (1 << 22) 92#define MMC1_PBIASLITE_VMODE (1 << 21) 93 94#ifndef __ASSEMBLY__ 95 96struct s32ktimer { 97 unsigned char res[0x10]; 98 unsigned int s32k_cr; /* 0x10 */ 99}; 100 101#define DEVICE_TYPE_SHIFT (0x8) 102#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 103 104#endif /* __ASSEMBLY__ */ 105 106/* 107 * Non-secure SRAM Addresses 108 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 109 * at 0x40304000(EMU base) so that our code works for both EMU and GP 110 */ 111#define NON_SECURE_SRAM_START 0x40304000 112#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 113#define NON_SECURE_SRAM_IMG_END 0x4030C000 114#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) 115/* base address for indirect vectors (internal boot mode) */ 116#define SRAM_ROM_VECT_BASE 0x4030D000 117 118/* ABB settings */ 119#define OMAP_ABB_SETTLING_TIME 50 120#define OMAP_ABB_CLOCK_CYCLES 16 121 122/* ABB tranxdone mask */ 123#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 124 125#define OMAP44XX_SAR_RAM_BASE 0x4a326000 126#define OMAP_REBOOT_REASON_OFFSET 0xA0C 127#define OMAP_REBOOT_REASON_SIZE 0x0F 128 129/* Boot parameters */ 130#ifndef __ASSEMBLY__ 131struct omap_boot_parameters { 132 unsigned int boot_message; 133 unsigned int boot_device_descriptor; 134 unsigned char boot_device; 135 unsigned char reset_reason; 136 unsigned char ch_flags; 137}; 138 139int omap_reboot_mode(char *mode, unsigned int length); 140int omap_reboot_mode_clear(void); 141int omap_reboot_mode_store(char *mode); 142#endif 143 144#endif 145