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7#ifndef _ASM_ARCH_DDR_RK3288_H
8#define _ASM_ARCH_DDR_RK3288_H
9
10struct rk3288_ddr_pctl {
11 u32 scfg;
12 u32 sctl;
13 u32 stat;
14 u32 intrstat;
15 u32 reserved0[12];
16 u32 mcmd;
17 u32 powctl;
18 u32 powstat;
19 u32 cmdtstat;
20 u32 tstaten;
21 u32 reserved1[3];
22 u32 mrrcfg0;
23 u32 mrrstat0;
24 u32 mrrstat1;
25 u32 reserved2[4];
26 u32 mcfg1;
27 u32 mcfg;
28 u32 ppcfg;
29 u32 mstat;
30 u32 lpddr2zqcfg;
31 u32 reserved3;
32 u32 dtupdes;
33 u32 dtuna;
34 u32 dtune;
35 u32 dtuprd0;
36 u32 dtuprd1;
37 u32 dtuprd2;
38 u32 dtuprd3;
39 u32 dtuawdt;
40 u32 reserved4[3];
41 u32 togcnt1u;
42 u32 tinit;
43 u32 trsth;
44 u32 togcnt100n;
45 u32 trefi;
46 u32 tmrd;
47 u32 trfc;
48 u32 trp;
49 u32 trtw;
50 u32 tal;
51 u32 tcl;
52 u32 tcwl;
53 u32 tras;
54 u32 trc;
55 u32 trcd;
56 u32 trrd;
57 u32 trtp;
58 u32 twr;
59 u32 twtr;
60 u32 texsr;
61 u32 txp;
62 u32 txpdll;
63 u32 tzqcs;
64 u32 tzqcsi;
65 u32 tdqs;
66 u32 tcksre;
67 u32 tcksrx;
68 u32 tcke;
69 u32 tmod;
70 u32 trstl;
71 u32 tzqcl;
72 u32 tmrr;
73 u32 tckesr;
74 u32 tdpd;
75 u32 reserved5[14];
76 u32 ecccfg;
77 u32 ecctst;
78 u32 eccclr;
79 u32 ecclog;
80 u32 reserved6[28];
81 u32 dtuwactl;
82 u32 dturactl;
83 u32 dtucfg;
84 u32 dtuectl;
85 u32 dtuwd0;
86 u32 dtuwd1;
87 u32 dtuwd2;
88 u32 dtuwd3;
89 u32 dtuwdm;
90 u32 dturd0;
91 u32 dturd1;
92 u32 dturd2;
93 u32 dturd3;
94 u32 dtulfsrwd;
95 u32 dtulfsrrd;
96 u32 dtueaf;
97 u32 dfitctrldelay;
98 u32 dfiodtcfg;
99 u32 dfiodtcfg1;
100 u32 dfiodtrankmap;
101 u32 dfitphywrdata;
102 u32 dfitphywrlat;
103 u32 reserved7[2];
104 u32 dfitrddataen;
105 u32 dfitphyrdlat;
106 u32 reserved8[2];
107 u32 dfitphyupdtype0;
108 u32 dfitphyupdtype1;
109 u32 dfitphyupdtype2;
110 u32 dfitphyupdtype3;
111 u32 dfitctrlupdmin;
112 u32 dfitctrlupdmax;
113 u32 dfitctrlupddly;
114 u32 reserved9;
115 u32 dfiupdcfg;
116 u32 dfitrefmski;
117 u32 dfitctrlupdi;
118 u32 reserved10[4];
119 u32 dfitrcfg0;
120 u32 dfitrstat0;
121 u32 dfitrwrlvlen;
122 u32 dfitrrdlvlen;
123 u32 dfitrrdlvlgateen;
124 u32 dfiststat0;
125 u32 dfistcfg0;
126 u32 dfistcfg1;
127 u32 reserved11;
128 u32 dfitdramclken;
129 u32 dfitdramclkdis;
130 u32 dfistcfg2;
131 u32 dfistparclr;
132 u32 dfistparlog;
133 u32 reserved12[3];
134 u32 dfilpcfg0;
135 u32 reserved13[3];
136 u32 dfitrwrlvlresp0;
137 u32 dfitrwrlvlresp1;
138 u32 dfitrwrlvlresp2;
139 u32 dfitrrdlvlresp0;
140 u32 dfitrrdlvlresp1;
141 u32 dfitrrdlvlresp2;
142 u32 dfitrwrlvldelay0;
143 u32 dfitrwrlvldelay1;
144 u32 dfitrwrlvldelay2;
145 u32 dfitrrdlvldelay0;
146 u32 dfitrrdlvldelay1;
147 u32 dfitrrdlvldelay2;
148 u32 dfitrrdlvlgatedelay0;
149 u32 dfitrrdlvlgatedelay1;
150 u32 dfitrrdlvlgatedelay2;
151 u32 dfitrcmd;
152 u32 reserved14[46];
153 u32 ipvr;
154 u32 iptr;
155};
156check_member(rk3288_ddr_pctl, iptr, 0x03fc);
157
158struct rk3288_ddr_publ_datx {
159 u32 dxgcr;
160 u32 dxgsr[2];
161 u32 dxdllcr;
162 u32 dxdqtr;
163 u32 dxdqstr;
164 u32 reserved[10];
165};
166
167struct rk3288_ddr_publ {
168 u32 ridr;
169 u32 pir;
170 u32 pgcr;
171 u32 pgsr;
172 u32 dllgcr;
173 u32 acdllcr;
174 u32 ptr[3];
175 u32 aciocr;
176 u32 dxccr;
177 u32 dsgcr;
178 u32 dcr;
179 u32 dtpr[3];
180 u32 mr[4];
181 u32 odtcr;
182 u32 dtar;
183 u32 dtdr[2];
184 u32 reserved1[24];
185 u32 dcuar;
186 u32 dcudr;
187 u32 dcurr;
188 u32 dculr;
189 u32 dcugcr;
190 u32 dcutpr;
191 u32 dcusr[2];
192 u32 reserved2[8];
193 u32 bist[17];
194 u32 reserved3[15];
195 u32 zq0cr[2];
196 u32 zq0sr[2];
197 u32 zq1cr[2];
198 u32 zq1sr[2];
199 u32 zq2cr[2];
200 u32 zq2sr[2];
201 u32 zq3cr[2];
202 u32 zq3sr[2];
203 struct rk3288_ddr_publ_datx datx8[4];
204};
205check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
206
207struct rk3288_msch {
208 u32 coreid;
209 u32 revisionid;
210 u32 ddrconf;
211 u32 ddrtiming;
212 u32 ddrmode;
213 u32 readlatency;
214 u32 reserved1[8];
215 u32 activate;
216 u32 devtodev;
217};
218check_member(rk3288_msch, devtodev, 0x003c);
219
220
221#define DFI_INIT_START (1 << 0)
222
223
224#define DFI_DRAM_CLK_SR_EN (1 << 0)
225#define DFI_DRAM_CLK_DPD_EN (1 << 1)
226
227
228#define DFI_PARITY_INTR_EN (1 << 0)
229#define DFI_PARITY_EN (1 << 1)
230
231
232#define TLP_RESP_TIME_SHIFT 16
233#define LP_SR_EN (1 << 8)
234#define LP_PD_EN (1 << 0)
235
236
237#define TCTRL_DELAY_TIME_SHIFT 0
238
239
240#define TPHY_WRDATA_TIME_SHIFT 0
241
242
243#define TPHY_RDLAT_TIME_SHIFT 0
244
245
246#define TDRAM_CLK_DIS_TIME_SHIFT 0
247
248
249#define TDRAM_CLK_EN_TIME_SHIFT 0
250
251
252#define RANK0_ODT_WRITE_SEL (1 << 3)
253#define RANK1_ODT_WRITE_SEL (1 << 11)
254
255
256#define ODT_LEN_BL8_W_SHIFT 16
257
258
259#define ACDLLCR_DLLDIS (1 << 31)
260#define ACDLLCR_DLLSRST (1 << 30)
261
262
263#define DXDLLCR_DLLDIS (1 << 31)
264#define DXDLLCR_DLLSRST (1 << 30)
265
266
267#define DLLGCR_SBIAS (1 << 30)
268
269
270#define DQSRTT (1 << 9)
271#define DQRTT (1 << 10)
272
273
274#define PIR_INIT (1 << 0)
275#define PIR_DLLSRST (1 << 1)
276#define PIR_DLLLOCK (1 << 2)
277#define PIR_ZCAL (1 << 3)
278#define PIR_ITMSRST (1 << 4)
279#define PIR_DRAMRST (1 << 5)
280#define PIR_DRAMINIT (1 << 6)
281#define PIR_QSTRN (1 << 7)
282#define PIR_RVTRN (1 << 8)
283#define PIR_ICPC (1 << 16)
284#define PIR_DLLBYP (1 << 17)
285#define PIR_CTLDINIT (1 << 18)
286#define PIR_CLRSR (1 << 28)
287#define PIR_LOCKBYP (1 << 29)
288#define PIR_ZCALBYP (1 << 30)
289#define PIR_INITBYP (1u << 31)
290
291
292#define PGCR_DFTLMT_SHIFT 3
293#define PGCR_DFTCMP_SHIFT 2
294#define PGCR_DQSCFG_SHIFT 1
295#define PGCR_ITMDMD_SHIFT 0
296
297
298#define PGSR_IDONE (1 << 0)
299#define PGSR_DLDONE (1 << 1)
300#define PGSR_ZCDONE (1 << 2)
301#define PGSR_DIDONE (1 << 3)
302#define PGSR_DTDONE (1 << 4)
303#define PGSR_DTERR (1 << 5)
304#define PGSR_DTIERR (1 << 6)
305#define PGSR_DFTERR (1 << 7)
306#define PGSR_RVERR (1 << 8)
307#define PGSR_RVEIRR (1 << 9)
308
309
310#define PRT_ITMSRST_SHIFT 18
311#define PRT_DLLLOCK_SHIFT 6
312#define PRT_DLLSRST_SHIFT 0
313
314
315#define PRT_DINIT0_SHIFT 0
316#define PRT_DINIT1_SHIFT 19
317
318
319#define PRT_DINIT2_SHIFT 0
320#define PRT_DINIT3_SHIFT 17
321
322
323#define DDRMD_LPDDR 0
324#define DDRMD_DDR 1
325#define DDRMD_DDR2 2
326#define DDRMD_DDR3 3
327#define DDRMD_LPDDR2_LPDDR3 4
328#define DDRMD_MASK 7
329#define DDRMD_SHIFT 0
330#define PDQ_MASK 7
331#define PDQ_SHIFT 4
332
333
334#define DQSNRES_MASK 0xf
335#define DQSNRES_SHIFT 8
336#define DQSRES_MASK 0xf
337#define DQSRES_SHIFT 4
338
339
340#define TDQSCKMAX_SHIFT 27
341#define TDQSCKMAX_MASK 7
342#define TDQSCK_SHIFT 24
343#define TDQSCK_MASK 7
344
345
346#define DQSGX_SHIFT 5
347#define DQSGX_MASK 7
348#define DQSGE_SHIFT 8
349#define DQSGE_MASK 7
350
351
352#define INIT_STATE 0
353#define CFG_STATE 1
354#define GO_STATE 2
355#define SLEEP_STATE 3
356#define WAKEUP_STATE 4
357
358
359#define LP_TRIG_SHIFT 4
360#define LP_TRIG_MASK 7
361#define PCTL_STAT_MSK 7
362#define INIT_MEM 0
363#define CONFIG 1
364#define CONFIG_REQ 2
365#define ACCESS 3
366#define ACCESS_REQ 4
367#define LOW_POWER 5
368#define LOW_POWER_ENTRY_REQ 6
369#define LOW_POWER_EXIT_REQ 7
370
371
372#define PD_OUTPUT_SHIFT 0
373#define PU_OUTPUT_SHIFT 5
374#define PD_ONDIE_SHIFT 10
375#define PU_ONDIE_SHIFT 15
376#define ZDEN_SHIFT 28
377
378
379#define SBIAS_BYPASS (1 << 23)
380
381
382#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
383#define PD_IDLE_SHIFT 8
384#define MDDR_EN (2 << 22)
385#define LPDDR2_EN (3 << 22)
386#define DDR2_EN (0 << 5)
387#define DDR3_EN (1 << 5)
388#define LPDDR2_S2 (0 << 6)
389#define LPDDR2_S4 (1 << 6)
390#define MDDR_LPDDR2_BL_2 (0 << 20)
391#define MDDR_LPDDR2_BL_4 (1 << 20)
392#define MDDR_LPDDR2_BL_8 (2 << 20)
393#define MDDR_LPDDR2_BL_16 (3 << 20)
394#define DDR2_DDR3_BL_4 0
395#define DDR2_DDR3_BL_8 1
396#define TFAW_SHIFT 18
397#define PD_EXIT_SLOW (0 << 17)
398#define PD_EXIT_FAST (1 << 17)
399#define PD_TYPE_SHIFT 16
400#define BURSTLENGTH_SHIFT 20
401
402
403#define POWER_UP_START (1 << 0)
404
405
406#define POWER_UP_DONE (1 << 0)
407
408
409enum {
410 DESELECT_CMD = 0,
411 PREA_CMD,
412 REF_CMD,
413 MRS_CMD,
414 ZQCS_CMD,
415 ZQCL_CMD,
416 RSTL_CMD,
417 MRR_CMD = 8,
418 DPDE_CMD,
419};
420
421#define LPDDR2_MA_SHIFT 4
422#define LPDDR2_MA_MASK 0xff
423#define LPDDR2_OP_SHIFT 12
424#define LPDDR2_OP_MASK 0xff
425
426#define START_CMD (1u << 31)
427
428
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430
431
432
433#define DDRCONF_ROW_SHIFT 4
434#define DDRCONF_COL_SHIFT 0
435
436
437#define BUSWRTORD_SHIFT 4
438#define BUSRDTOWR_SHIFT 2
439#define BUSRDTORD_SHIFT 0
440
441
442#define DDR3_DLL_DISABLE 1
443
444#endif
445
