LXR uboot/board/renesas/gose/gose.c

   1/*
   2 * board/renesas/gose/gose.c
   3 *
   4 * Copyright (C) 2014 Renesas Electronics Corporation
   5 *
   6 * SPDX-License-Identifier: GPL-2.0
   7 */
   8
   9#include <common.h>
  10#include <malloc.h>
  11#include <dm.h>
  12#include <dm/platform_data/serial_sh.h>
  13#include <asm/processor.h>
  14#include <asm/mach-types.h>
  15#include <asm/io.h>
  16#include <linux/errno.h>
  17#include <asm/arch/sys_proto.h>
  18#include <asm/gpio.h>
  19#include <asm/arch/rmobile.h>
  20#include <asm/arch/rcar-mstp.h>
  21#include <asm/arch/sh_sdhi.h>
  22#include <netdev.h>
  23#include <miiphy.h>
  24#include <i2c.h>
  25#include "qos.h"
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29#define CLK2MHZ(clk)    (clk / 1000 / 1000)
  30void s_init(void)
  31{
  32        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  33        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  34        u32 stc;
  35
  36        /* Watchdog init */
  37        writel(0xA5A5A500, &rwdt->rwtcsra);
  38        writel(0xA5A5A500, &swdt->swtcsra);
  39
  40        /* CPU frequency setting. Set to 1.5GHz */
  41        stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  42        clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  43
  44        /* QoS */
  45        qos_init();
  46}
  47
  48#define TMU0_MSTP125    (1 << 25)
  49#define SCIF0_MSTP721   (1 << 21)
  50#define ETHER_MSTP813   (1 << 13)
  51
  52#define SDHI0_MSTP314   (1 << 14)
  53#define SDHI1_MSTP312   (1 << 12)
  54#define SDHI2_MSTP311   (1 << 11)
  55
  56#define SD1CKCR         0xE6150078
  57#define SD2CKCR         0xE615026C
  58#define SD_97500KHZ     0x7
  59
  60int board_early_init_f(void)
  61{
  62        /* TMU0 */
  63        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  64
  65        /* SCIF0 */
  66        mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
  67
  68        /* ETHER */
  69        mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  70
  71        /* SDHI */
  72        mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
  73                          SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
  74        writel(SD_97500KHZ, SD1CKCR);
  75        writel(SD_97500KHZ, SD2CKCR);
  76
  77        return 0;
  78}
  79
  80#define PUPR5           0xE6060114
  81#define PUPR5_ETH       0x3FFC0000
  82#define PUPR5_ETH_MAGIC (1 << 27)
  83
  84int board_init(void)
  85{
  86        /* adress of boot parameters */
  87        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  88
  89        /* Init PFC controller */
  90        r8a7793_pinmux_init();
  91
  92        /* ETHER Enable */
  93        gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  94        gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  95        gpio_request(GPIO_FN_ETH_RXD0, NULL);
  96        gpio_request(GPIO_FN_ETH_RXD1, NULL);
  97        gpio_request(GPIO_FN_ETH_LINK, NULL);
  98        gpio_request(GPIO_FN_ETH_REFCLK, NULL);
  99        gpio_request(GPIO_FN_ETH_MDIO, NULL);
 100        gpio_request(GPIO_FN_ETH_TXD1, NULL);
 101        gpio_request(GPIO_FN_ETH_TX_EN, NULL);
 102        gpio_request(GPIO_FN_ETH_TXD0, NULL);
 103        gpio_request(GPIO_FN_ETH_MDC, NULL);
 104        gpio_request(GPIO_FN_IRQ0, NULL);
 105
 106        mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
 107        gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
 108        mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
 109
 110        gpio_direction_output(GPIO_GP_5_22, 0);
 111        mdelay(20);
 112        gpio_set_value(GPIO_GP_5_22, 1);
 113        udelay(1);
 114
 115        return 0;
 116}
 117
 118#define CXR24 0xEE7003C0 /* MAC address high register */
 119#define CXR25 0xEE7003C8 /* MAC address low register */
 120
 121int board_eth_init(bd_t *bis)
 122{
 123        int ret = -ENODEV;
 124        u32 val;
 125        unsigned char enetaddr[6];
 126
 127#ifdef CONFIG_SH_ETHER
 128        ret = sh_eth_initialize(bis);
 129        if (!eth_env_get_enetaddr("ethaddr", enetaddr))
 130                return ret;
 131
 132        /* Set Mac address */
 133        val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 134            enetaddr[2] << 8 | enetaddr[3];
 135        writel(val, CXR24);
 136
 137        val = enetaddr[4] << 8 | enetaddr[5];
 138        writel(val, CXR25);
 139#endif
 140
 141        return ret;
 142}
 143
 144int board_mmc_init(bd_t *bis)
 145{
 146        int ret = -ENODEV;
 147
 148#ifdef CONFIG_SH_SDHI
 149        gpio_request(GPIO_FN_SD0_DATA0, NULL);
 150        gpio_request(GPIO_FN_SD0_DATA1, NULL);
 151        gpio_request(GPIO_FN_SD0_DATA2, NULL);
 152        gpio_request(GPIO_FN_SD0_DATA3, NULL);
 153        gpio_request(GPIO_FN_SD0_CLK, NULL);
 154        gpio_request(GPIO_FN_SD0_CMD, NULL);
 155        gpio_request(GPIO_FN_SD0_CD, NULL);
 156        gpio_request(GPIO_FN_SD2_DATA0, NULL);
 157        gpio_request(GPIO_FN_SD2_DATA1, NULL);
 158        gpio_request(GPIO_FN_SD2_DATA2, NULL);
 159        gpio_request(GPIO_FN_SD2_DATA3, NULL);
 160        gpio_request(GPIO_FN_SD2_CLK, NULL);
 161        gpio_request(GPIO_FN_SD2_CMD, NULL);
 162        gpio_request(GPIO_FN_SD2_CD, NULL);
 163
 164        /* SDHI 0 */
 165        gpio_request(GPIO_GP_7_17, NULL);
 166        gpio_request(GPIO_GP_2_12, NULL);
 167        gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
 168        gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
 169
 170        ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
 171                           SH_SDHI_QUIRK_16BIT_BUF);
 172        if (ret)
 173                return ret;
 174
 175        /* SDHI 1 */
 176        gpio_request(GPIO_GP_7_18, NULL);
 177        gpio_request(GPIO_GP_2_13, NULL);
 178        gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
 179        gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
 180
 181        ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
 182        if (ret)
 183                return ret;
 184
 185        /* SDHI 2 */
 186        gpio_request(GPIO_GP_7_19, NULL);
 187        gpio_request(GPIO_GP_2_26, NULL);
 188        gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
 189        gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
 190
 191        ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
 192#endif
 193        return ret;
 194}
 195
 196int dram_init(void)
 197{
 198        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 199
 200        return 0;
 201}
 202
 203const struct rmobile_sysinfo sysinfo = {
 204        CONFIG_ARCH_RMOBILE_BOARD_STRING
 205};
 206
 207void reset_cpu(ulong addr)
 208{
 209        u8 val;
 210
 211        i2c_set_bus_num(2); /* PowerIC connected to ch2 */
 212        i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 213        val |= 0x02;
 214        i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 215}
 216
 217static const struct sh_serial_platdata serial_platdata = {
 218        .base = SCIF0_BASE,
 219        .type = PORT_SCIF,
 220        .clk = 14745600,
 221        .clk_mode = EXT_CLK,
 222};
 223
 224U_BOOT_DEVICE(gose_serials) = {
 225        .name = "serial_sh",
 226        .platdata = &serial_platdata,
 227};
 228