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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <asm/config_mpc85xx.h>
15#define CONFIG_NAND_FSL_IFC
16
17#ifdef CONFIG_SDCARD
18#define CONFIG_SPL_MMC_MINIMAL
19#define CONFIG_SPL_FLUSH_IMAGE
20#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21#define CONFIG_SYS_TEXT_BASE 0x11001000
22#define CONFIG_SPL_TEXT_BASE 0xD0001000
23#define CONFIG_SPL_PAD_TO 0x18000
24#define CONFIG_SPL_MAX_SIZE (96 * 1024)
25#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
26#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
28#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
29#define CONFIG_SYS_MPC85XX_NO_RESETVEC
30#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
31#define CONFIG_SPL_MMC_BOOT
32#ifdef CONFIG_SPL_BUILD
33#define CONFIG_SPL_COMMON_INIT_DDR
34#endif
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#ifdef CONFIG_SECURE_BOOT
39#define CONFIG_RAMBOOT_SPIFLASH
40#define CONFIG_SYS_TEXT_BASE 0x11000000
41#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
42#else
43#define CONFIG_SPL_SPI_FLASH_MINIMAL
44#define CONFIG_SPL_FLUSH_IMAGE
45#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46#define CONFIG_SYS_TEXT_BASE 0x11001000
47#define CONFIG_SPL_TEXT_BASE 0xD0001000
48#define CONFIG_SPL_PAD_TO 0x18000
49#define CONFIG_SPL_MAX_SIZE (96 * 1024)
50#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
51#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
52#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
53#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
54#define CONFIG_SYS_MPC85XX_NO_RESETVEC
55#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
56#define CONFIG_SPL_SPI_BOOT
57#ifdef CONFIG_SPL_BUILD
58#define CONFIG_SPL_COMMON_INIT_DDR
59#endif
60#endif
61#endif
62
63#ifdef CONFIG_NAND
64#ifdef CONFIG_SECURE_BOOT
65#define CONFIG_SPL_INIT_MINIMAL
66#define CONFIG_SPL_NAND_BOOT
67#define CONFIG_SPL_FLUSH_IMAGE
68#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69
70#define CONFIG_SYS_TEXT_BASE 0x00201000
71#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
72#define CONFIG_SPL_MAX_SIZE 8192
73#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
74#define CONFIG_SPL_RELOC_STACK 0x00100000
75#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
76#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
77#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
78#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
79#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
80#else
81#ifdef CONFIG_TPL_BUILD
82#define CONFIG_SPL_NAND_BOOT
83#define CONFIG_SPL_FLUSH_IMAGE
84#define CONFIG_SPL_NAND_INIT
85#define CONFIG_SPL_COMMON_INIT_DDR
86#define CONFIG_SPL_MAX_SIZE (128 << 10)
87#define CONFIG_SPL_TEXT_BASE 0xD0001000
88#define CONFIG_SYS_MPC85XX_NO_RESETVEC
89#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
90#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
91#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
92#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
93#elif defined(CONFIG_SPL_BUILD)
94#define CONFIG_SPL_INIT_MINIMAL
95#define CONFIG_SPL_NAND_MINIMAL
96#define CONFIG_SPL_FLUSH_IMAGE
97#define CONFIG_SPL_TEXT_BASE 0xff800000
98#define CONFIG_SPL_MAX_SIZE 8192
99#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
100#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
101#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
102#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
103#endif
104#define CONFIG_SPL_PAD_TO 0x20000
105#define CONFIG_TPL_PAD_TO 0x20000
106#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
107#define CONFIG_SYS_TEXT_BASE 0x11001000
108#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109#endif
110#endif
111
112#ifdef CONFIG_NAND_SECBOOT
113#define CONFIG_RAMBOOT_NAND
114#define CONFIG_SYS_TEXT_BASE 0x11000000
115#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
116#endif
117
118#ifndef CONFIG_SYS_TEXT_BASE
119#define CONFIG_SYS_TEXT_BASE 0xeff40000
120#endif
121
122#ifndef CONFIG_RESET_VECTOR_ADDRESS
123#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124#endif
125
126#ifdef CONFIG_SPL_BUILD
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
128#else
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
130#endif
131
132
133#define CONFIG_SYS_HAS_SERDES
134
135#if defined(CONFIG_PCI)
136#define CONFIG_PCIE1
137#define CONFIG_PCIE2
138#define CONFIG_FSL_PCI_INIT
139#define CONFIG_PCI_INDIRECT_BRIDGE
140#define CONFIG_FSL_PCIE_RESET
141#define CONFIG_SYS_PCI_64BIT
142
143
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145
146
147
148#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
149#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
150#ifdef CONFIG_PHYS_64BIT
151#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
152#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
153#else
154#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
155#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
156#endif
157#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
158#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
159#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
160#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
161#ifdef CONFIG_PHYS_64BIT
162#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
163#else
164#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
165#endif
166
167
168#if defined(CONFIG_TARGET_P1010RDB_PA)
169#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
170#elif defined(CONFIG_TARGET_P1010RDB_PB)
171#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
172#endif
173#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
174#ifdef CONFIG_PHYS_64BIT
175#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
176#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
177#else
178#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
179#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
180#endif
181#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
182#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
183#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
184#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
185#ifdef CONFIG_PHYS_64BIT
186#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
187#else
188#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
189#endif
190
191#define CONFIG_PCI_SCAN_SHOW
192#endif
193
194#define CONFIG_TSEC_ENET
195#define CONFIG_ENV_OVERWRITE
196
197#define CONFIG_DDR_CLK_FREQ 66666666
198#define CONFIG_SYS_CLK_FREQ 66666666
199
200#define CONFIG_MISC_INIT_R
201#define CONFIG_HWCONFIG
202
203
204
205#define CONFIG_L2_CACHE
206#define CONFIG_BTB
207
208
209#define CONFIG_ENABLE_36BIT_PHYS
210
211#ifdef CONFIG_PHYS_64BIT
212#define CONFIG_ADDR_MAP 1
213#define CONFIG_SYS_NUM_ADDR_MAP 16
214#endif
215
216#define CONFIG_SYS_MEMTEST_START 0x00200000
217#define CONFIG_SYS_MEMTEST_END 0x1fffffff
218
219
220#define CONFIG_SYS_DDR_RAW_TIMING
221#define CONFIG_DDR_SPD
222#define CONFIG_SYS_SPD_BUS_NUM 1
223#define SPD_EEPROM_ADDRESS 0x52
224
225#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
226
227#ifndef __ASSEMBLY__
228extern unsigned long get_sdram_size(void);
229#endif
230#define CONFIG_SYS_SDRAM_SIZE get_sdram_size()
231#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
232#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
233
234#define CONFIG_DIMM_SLOTS_PER_CTLR 1
235#define CONFIG_CHIP_SELECTS_PER_CTRL 1
236
237
238#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
239#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
240#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
241#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
242#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
243#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
244#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
245#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
246#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
247#define CONFIG_SYS_DDR_RCW_1 0x00000000
248#define CONFIG_SYS_DDR_RCW_2 0x00000000
249#define CONFIG_SYS_DDR_CONTROL 0xc70c0008
250#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
251#define CONFIG_SYS_DDR_TIMING_4 0x00000001
252#define CONFIG_SYS_DDR_TIMING_5 0x03402400
253
254#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
255#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
256#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
257#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
258#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
259#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
260#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
261#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
262#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
263
264
265#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
266#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
267#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
268#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
269#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
270#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
271#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
272#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
273#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
274
275#define CONFIG_SYS_CCSRBAR 0xffe00000
276#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
277
278
279#ifdef CONFIG_SPL_BUILD
280#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
281#endif
282
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300
301
302#define CONFIG_SYS_FLASH_BASE 0xee000000
303#define CONFIG_SYS_MAX_FLASH_SECT 256
304
305#ifdef CONFIG_PHYS_64BIT
306#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
307#else
308#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
309#endif
310
311#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
312 CSPR_PORT_SIZE_16 | \
313 CSPR_MSEL_NOR | \
314 CSPR_V)
315#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
316#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
317
318#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
319 FTIM0_NOR_TEADC(0x5) | \
320 FTIM0_NOR_TEAHC(0x5)
321#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
322 FTIM1_NOR_TRAD_NOR(0x0f)
323#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
324 FTIM2_NOR_TCH(0x4) | \
325 FTIM2_NOR_TWP(0x1c)
326#define CONFIG_SYS_NOR_FTIM3 0x0
327
328#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
329#define CONFIG_SYS_FLASH_QUIET_TEST
330#define CONFIG_FLASH_SHOW_PROGRESS 45
331#define CONFIG_SYS_MAX_FLASH_BANKS 1
332
333#undef CONFIG_SYS_FLASH_CHECKSUM
334#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
335#define CONFIG_SYS_FLASH_WRITE_TOUT 500
336
337
338#define CONFIG_FLASH_CFI_DRIVER
339#define CONFIG_SYS_FLASH_CFI
340#define CONFIG_SYS_FLASH_EMPTY_INFO
341#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
342
343
344#define CONFIG_SYS_NAND_BASE 0xff800000
345#ifdef CONFIG_PHYS_64BIT
346#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
347#else
348#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
349#endif
350
351#define CONFIG_MTD_DEVICE
352#define CONFIG_MTD_PARTITION
353
354#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
355 | CSPR_PORT_SIZE_8 \
356 | CSPR_MSEL_NAND \
357 | CSPR_V)
358#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
359
360#if defined(CONFIG_TARGET_P1010RDB_PA)
361#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
362 | CSOR_NAND_ECC_DEC_EN \
363 | CSOR_NAND_ECC_MODE_4 \
364 | CSOR_NAND_RAL_2 \
365 | CSOR_NAND_PGS_512 \
366 | CSOR_NAND_SPRZ_16 \
367 | CSOR_NAND_PB(32))
368#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
369
370#elif defined(CONFIG_TARGET_P1010RDB_PB)
371#define CONFIG_SYS_NAND_ONFI_DETECTION
372#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
373 | CSOR_NAND_ECC_DEC_EN \
374 | CSOR_NAND_ECC_MODE_4 \
375 | CSOR_NAND_RAL_3 \
376 | CSOR_NAND_PGS_4K \
377 | CSOR_NAND_SPRZ_224 \
378 | CSOR_NAND_PB(128))
379#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
380#endif
381
382#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
383#define CONFIG_SYS_MAX_NAND_DEVICE 1
384
385#if defined(CONFIG_TARGET_P1010RDB_PA)
386
387#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
388 FTIM0_NAND_TWP(0x0C) | \
389 FTIM0_NAND_TWCHT(0x04) | \
390 FTIM0_NAND_TWH(0x05)
391#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
392 FTIM1_NAND_TWBE(0x1d) | \
393 FTIM1_NAND_TRR(0x07) | \
394 FTIM1_NAND_TRP(0x0c)
395#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
396 FTIM2_NAND_TREH(0x05) | \
397 FTIM2_NAND_TWHRE(0x0f)
398#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
399
400#elif defined(CONFIG_TARGET_P1010RDB_PB)
401
402
403#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
404 FTIM0_NAND_TWP(0x18) | \
405 FTIM0_NAND_TWCHT(0x07) | \
406 FTIM0_NAND_TWH(0x0a))
407#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
408 FTIM1_NAND_TWBE(0x39) | \
409 FTIM1_NAND_TRR(0x0e) | \
410 FTIM1_NAND_TRP(0x18))
411#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
412 FTIM2_NAND_TREH(0x0a) | \
413 FTIM2_NAND_TWHRE(0x1e))
414#define CONFIG_SYS_NAND_FTIM3 0x0
415#endif
416
417#define CONFIG_SYS_NAND_DDR_LAW 11
418
419
420#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
421#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
422#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
423#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
424#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
425#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
426#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
427#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
428#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
429#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
430#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
431#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
432#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
433#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
434#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
435#else
436#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
437#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
438#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
439#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
440#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
441#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
442#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
443#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
444#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
445#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
446#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
447#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
448#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
449#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
450#endif
451
452
453#define CONFIG_SYS_CPLD_BASE 0xffb00000
454
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
457#else
458#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
459#endif
460
461#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
462 | CSPR_PORT_SIZE_8 \
463 | CSPR_MSEL_GPCM \
464 | CSPR_V)
465#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
466#define CONFIG_SYS_CSOR3 0x0
467
468#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
469 FTIM0_GPCM_TEADC(0x0e) | \
470 FTIM0_GPCM_TEAHC(0x0e))
471#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
472 FTIM1_GPCM_TRAD(0x1f))
473#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
474 FTIM2_GPCM_TCH(0x8) | \
475 FTIM2_GPCM_TWP(0x1f))
476#define CONFIG_SYS_CS3_FTIM3 0x0
477
478#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
479 defined(CONFIG_RAMBOOT_NAND)
480#define CONFIG_SYS_RAMBOOT
481#define CONFIG_SYS_EXTRA_ENV_RELOC
482#else
483#undef CONFIG_SYS_RAMBOOT
484#endif
485
486#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
487#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
488#define CONFIG_A003399_NOR_WORKAROUND
489#endif
490#endif
491
492#define CONFIG_BOARD_EARLY_INIT_R
493
494#define CONFIG_SYS_INIT_RAM_LOCK
495#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
496#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
497
498#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
499 - GENERATED_GBL_DATA_SIZE)
500#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
501
502#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
503#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
504
505
506
507
508#if defined(CONFIG_SPL_BUILD)
509#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
510#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
511#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
512#define CONFIG_SYS_L2_SIZE (256 << 10)
513#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
514#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
515#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
516#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
517#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
518#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
519#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
520#elif defined(CONFIG_NAND)
521#ifdef CONFIG_TPL_BUILD
522#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
523#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
524#define CONFIG_SYS_L2_SIZE (256 << 10)
525#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
526#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
527#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
528#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
529#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
530#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
531#else
532#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
533#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
534#define CONFIG_SYS_L2_SIZE (256 << 10)
535#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
536#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
537#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
538#endif
539#endif
540#endif
541
542
543#define CONFIG_CONS_INDEX 1
544#undef CONFIG_SERIAL_SOFTWARE_FIFO
545#define CONFIG_SYS_NS16550_SERIAL
546#define CONFIG_SYS_NS16550_REG_SIZE 1
547#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
548#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
549#define CONFIG_NS16550_MIN_FUNCTIONS
550#endif
551
552#define CONFIG_SYS_BAUDRATE_TABLE \
553 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
554
555#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
556#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
557
558
559#define CONFIG_SYS_I2C
560#define CONFIG_SYS_I2C_FSL
561#define CONFIG_SYS_FSL_I2C_SPEED 400000
562#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
563#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
564#define CONFIG_SYS_FSL_I2C2_SPEED 400000
565#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
566#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
567#define I2C_PCA9557_ADDR1 0x18
568#define I2C_PCA9557_ADDR2 0x19
569#define I2C_PCA9557_BUS_NUM 0
570
571
572#if defined(CONFIG_TARGET_P1010RDB_PB)
573#define CONFIG_ID_EEPROM
574#ifdef CONFIG_ID_EEPROM
575#define CONFIG_SYS_I2C_EEPROM_NXID
576#endif
577#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
578#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
579#define CONFIG_SYS_EEPROM_BUS_NUM 0
580#define MAX_NUM_PORTS 9
581#endif
582
583#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
584#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
585#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
586
587
588#define CONFIG_RTC_PT7C4338
589#define CONFIG_SYS_I2C_RTC_ADDR 0x68
590
591
592
593
594
595#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
596
597#define CONFIG_SF_DEFAULT_SPEED 10000000
598#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
599#endif
600
601#if defined(CONFIG_TSEC_ENET)
602#define CONFIG_MII
603#define CONFIG_MII_DEFAULT_TSEC 1
604#define CONFIG_TSEC1 1
605#define CONFIG_TSEC1_NAME "eTSEC1"
606#define CONFIG_TSEC2 1
607#define CONFIG_TSEC2_NAME "eTSEC2"
608#define CONFIG_TSEC3 1
609#define CONFIG_TSEC3_NAME "eTSEC3"
610
611#define TSEC1_PHY_ADDR 1
612#define TSEC2_PHY_ADDR 0
613#define TSEC3_PHY_ADDR 2
614
615#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
616#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
617#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
618
619#define TSEC1_PHYIDX 0
620#define TSEC2_PHYIDX 0
621#define TSEC3_PHYIDX 0
622
623#define CONFIG_ETHPRIME "eTSEC1"
624
625
626#define CONFIG_TSEC_TBICR_SETTINGS ( \
627 TBICR_PHY_RESET \
628 | TBICR_ANEG_ENABLE \
629 | TBICR_FULL_DUPLEX \
630 | TBICR_SPEED1_SET \
631 )
632
633#endif
634
635
636#define CONFIG_FSL_SATA_V2
637
638#ifdef CONFIG_FSL_SATA
639#define CONFIG_SYS_SATA_MAX_DEVICE 2
640#define CONFIG_SATA1
641#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
642#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
643#define CONFIG_SATA2
644#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
645#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
646
647#define CONFIG_LBA48
648#endif
649
650#ifdef CONFIG_MMC
651#define CONFIG_FSL_ESDHC
652#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
653#endif
654
655#define CONFIG_HAS_FSL_DR_USB
656
657#if defined(CONFIG_HAS_FSL_DR_USB)
658#ifdef CONFIG_USB_EHCI_HCD
659#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
660#define CONFIG_USB_EHCI_FSL
661#endif
662#endif
663
664
665
666
667#if defined(CONFIG_SDCARD)
668#define CONFIG_FSL_FIXED_MMC_LOCATION
669#define CONFIG_SYS_MMC_ENV_DEV 0
670#define CONFIG_ENV_SIZE 0x2000
671#elif defined(CONFIG_SPIFLASH)
672#define CONFIG_ENV_SPI_BUS 0
673#define CONFIG_ENV_SPI_CS 0
674#define CONFIG_ENV_SPI_MAX_HZ 10000000
675#define CONFIG_ENV_SPI_MODE 0
676#define CONFIG_ENV_OFFSET 0x100000
677#define CONFIG_ENV_SECT_SIZE 0x10000
678#define CONFIG_ENV_SIZE 0x2000
679#elif defined(CONFIG_NAND)
680#ifdef CONFIG_TPL_BUILD
681#define CONFIG_ENV_SIZE 0x2000
682#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
683#else
684#if defined(CONFIG_TARGET_P1010RDB_PA)
685#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
686#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
687#elif defined(CONFIG_TARGET_P1010RDB_PB)
688#define CONFIG_ENV_SIZE (16 * 1024)
689#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE)
690#endif
691#endif
692#define CONFIG_ENV_OFFSET (1024 * 1024)
693#elif defined(CONFIG_SYS_RAMBOOT)
694#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
695#define CONFIG_ENV_SIZE 0x2000
696#else
697#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
698#define CONFIG_ENV_SIZE 0x2000
699#define CONFIG_ENV_SECT_SIZE 0x20000
700#endif
701
702#define CONFIG_LOADS_ECHO
703#define CONFIG_SYS_LOADS_BAUD_CHANGE
704
705#undef CONFIG_WATCHDOG
706
707#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
708 || defined(CONFIG_FSL_SATA)
709#endif
710
711
712
713
714#define CONFIG_SYS_LONGHELP
715#define CONFIG_CMDLINE_EDITING
716#define CONFIG_AUTO_COMPLETE
717#define CONFIG_SYS_LOAD_ADDR 0x2000000
718
719
720
721
722
723
724#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
725#define CONFIG_SYS_BOOTM_LEN (64 << 20)
726
727#if defined(CONFIG_CMD_KGDB)
728#define CONFIG_KGDB_BAUDRATE 230400
729#endif
730
731
732
733
734
735#if defined(CONFIG_TSEC_ENET)
736#define CONFIG_HAS_ETH0
737#define CONFIG_HAS_ETH1
738#define CONFIG_HAS_ETH2
739#endif
740
741#define CONFIG_ROOTPATH "/opt/nfsroot"
742#define CONFIG_BOOTFILE "uImage"
743#define CONFIG_UBOOTPATH u-boot.bin
744
745
746#define CONFIG_LOADADDR 1000000
747
748#define CONFIG_EXTRA_ENV_SETTINGS \
749 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
750 "netdev=eth0\0" \
751 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
752 "loadaddr=1000000\0" \
753 "consoledev=ttyS0\0" \
754 "ramdiskaddr=2000000\0" \
755 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
756 "fdtaddr=1e00000\0" \
757 "fdtfile=p1010rdb.dtb\0" \
758 "bdev=sda1\0" \
759 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
760 "othbootargs=ramdisk_size=600000\0" \
761 "usbfatboot=setenv bootargs root=/dev/ram rw " \
762 "console=$consoledev,$baudrate $othbootargs; " \
763 "usb start;" \
764 "fatload usb 0:2 $loadaddr $bootfile;" \
765 "fatload usb 0:2 $fdtaddr $fdtfile;" \
766 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
767 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
768 "usbext2boot=setenv bootargs root=/dev/ram rw " \
769 "console=$consoledev,$baudrate $othbootargs; " \
770 "usb start;" \
771 "ext2load usb 0:4 $loadaddr $bootfile;" \
772 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
773 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
774 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
775 CONFIG_BOOTMODE
776
777#if defined(CONFIG_TARGET_P1010RDB_PA)
778#define CONFIG_BOOTMODE \
779 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
780 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
781 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
782 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
783 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
784 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
785
786#elif defined(CONFIG_TARGET_P1010RDB_PB)
787#define CONFIG_BOOTMODE \
788 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
789 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
790 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
791 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
792 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
793 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
794 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
795 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
796 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
797 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
798#endif
799
800#define CONFIG_RAMBOOTCOMMAND \
801 "setenv bootargs root=/dev/ram rw " \
802 "console=$consoledev,$baudrate $othbootargs; " \
803 "tftp $ramdiskaddr $ramdiskfile;" \
804 "tftp $loadaddr $bootfile;" \
805 "tftp $fdtaddr $fdtfile;" \
806 "bootm $loadaddr $ramdiskaddr $fdtaddr"
807
808#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
809
810#include <asm/fsl_secure_boot.h>
811
812#endif
813