LXR uboot/arch/arm/mach-aspeed/ast2500-board.c

   1/*
   2 * Copyright (c) 2016 Google, Inc
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6#include <common.h>
   7#include <dm.h>
   8#include <ram.h>
   9#include <timer.h>
  10#include <asm/io.h>
  11#include <asm/arch/timer.h>
  12#include <asm/arch/wdt.h>
  13#include <linux/err.h>
  14#include <dm/uclass.h>
  15
  16/*
  17 * Second Watchdog Timer by default is configured
  18 * to trigger secondary boot source.
  19 */
  20#define AST_2ND_BOOT_WDT                1
  21
  22/*
  23 * Third Watchdog Timer by default is configured
  24 * to toggle Flash address mode switch before reset.
  25 */
  26#define AST_FLASH_ADDR_DETECT_WDT       2
  27
  28DECLARE_GLOBAL_DATA_PTR;
  29
  30void lowlevel_init(void)
  31{
  32        /*
  33         * These two watchdogs need to be stopped as soon as possible,
  34         * otherwise the board might hang. By default they are set to
  35         * a very short timeout and even simple debug write to serial
  36         * console early in the init process might cause them to fire.
  37         */
  38        struct ast_wdt *flash_addr_wdt =
  39            (struct ast_wdt *)(WDT_BASE +
  40                               sizeof(struct ast_wdt) *
  41                               AST_FLASH_ADDR_DETECT_WDT);
  42
  43        clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
  44
  45#ifndef CONFIG_FIRMWARE_2ND_BOOT
  46        struct ast_wdt *sec_boot_wdt =
  47            (struct ast_wdt *)(WDT_BASE +
  48                               sizeof(struct ast_wdt) *
  49                               AST_2ND_BOOT_WDT);
  50
  51        clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
  52#endif
  53}
  54
  55int board_init(void)
  56{
  57        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  58
  59        return 0;
  60}
  61
  62int dram_init(void)
  63{
  64        struct udevice *dev;
  65        struct ram_info ram;
  66        int ret;
  67
  68        ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  69        if (ret) {
  70                debug("DRAM FAIL1\r\n");
  71                return ret;
  72        }
  73
  74        ret = ram_get_info(dev, &ram);
  75        if (ret) {
  76                debug("DRAM FAIL2\r\n");
  77                return ret;
  78        }
  79
  80        gd->ram_size = ram.size;
  81
  82        return 0;
  83}
  84