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8#ifndef RISCV_CSR_ENCODING_H
9#define RISCV_CSR_ENCODING_H
10
11#define MSTATUS_UIE 0x00000001
12#define MSTATUS_SIE 0x00000002
13#define MSTATUS_HIE 0x00000004
14#define MSTATUS_MIE 0x00000008
15#define MSTATUS_UPIE 0x00000010
16#define MSTATUS_SPIE 0x00000020
17#define MSTATUS_HPIE 0x00000040
18#define MSTATUS_MPIE 0x00000080
19#define MSTATUS_SPP 0x00000100
20#define MSTATUS_HPP 0x00000600
21#define MSTATUS_MPP 0x00001800
22#define MSTATUS_FS 0x00006000
23#define MSTATUS_XS 0x00018000
24#define MSTATUS_MPRV 0x00020000
25#define MSTATUS_PUM 0x00040000
26#define MSTATUS_VM 0x1F000000
27#define MSTATUS32_SD 0x80000000
28#define MSTATUS64_SD 0x8000000000000000
29
30#define MCAUSE32_CAUSE 0x7FFFFFFF
31#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
32#define MCAUSE32_INT 0x80000000
33#define MCAUSE64_INT 0x8000000000000000
34
35#define SSTATUS_UIE 0x00000001
36#define SSTATUS_SIE 0x00000002
37#define SSTATUS_UPIE 0x00000010
38#define SSTATUS_SPIE 0x00000020
39#define SSTATUS_SPP 0x00000100
40#define SSTATUS_FS 0x00006000
41#define SSTATUS_XS 0x00018000
42#define SSTATUS_PUM 0x00040000
43#define SSTATUS32_SD 0x80000000
44#define SSTATUS64_SD 0x8000000000000000
45
46#define MIP_SSIP BIT(IRQ_S_SOFT)
47#define MIP_HSIP BIT(IRQ_H_SOFT)
48#define MIP_MSIP BIT(IRQ_M_SOFT)
49#define MIP_STIP BIT(IRQ_S_TIMER)
50#define MIP_HTIP BIT(IRQ_H_TIMER)
51#define MIP_MTIP BIT(IRQ_M_TIMER)
52#define MIP_SEIP BIT(IRQ_S_EXT)
53#define MIP_HEIP BIT(IRQ_H_EXT)
54#define MIP_MEIP BIT(IRQ_M_EXT)
55
56#define SIP_SSIP MIP_SSIP
57#define SIP_STIP MIP_STIP
58
59#define PRV_U 0
60#define PRV_S 1
61#define PRV_H 2
62#define PRV_M 3
63
64#define VM_MBARE 0
65#define VM_MBB 1
66#define VM_MBBID 2
67#define VM_SV32 8
68#define VM_SV39 9
69#define VM_SV48 10
70
71#define IRQ_S_SOFT 1
72#define IRQ_H_SOFT 2
73#define IRQ_M_SOFT 3
74#define IRQ_S_TIMER 5
75#define IRQ_H_TIMER 6
76#define IRQ_M_TIMER 7
77#define IRQ_S_EXT 9
78#define IRQ_H_EXT 10
79#define IRQ_M_EXT 11
80#define IRQ_COP 12
81#define IRQ_HOST 13
82
83#define DEFAULT_RSTVEC 0x00001000
84#define DEFAULT_NMIVEC 0x00001004
85#define DEFAULT_MTVEC 0x00001010
86#define CONFIG_STRING_ADDR 0x0000100C
87#define EXT_IO_BASE 0x40000000
88#define DRAM_BASE 0x80000000
89
90
91#define PTE_V 0x001
92#define PTE_TYPE 0x01E
93#define PTE_R 0x020
94#define PTE_D 0x040
95#define PTE_SOFT 0x380
96
97#define PTE_TYPE_TABLE 0x00
98#define PTE_TYPE_TABLE_GLOBAL 0x02
99#define PTE_TYPE_URX_SR 0x04
100#define PTE_TYPE_URWX_SRW 0x06
101#define PTE_TYPE_UR_SR 0x08
102#define PTE_TYPE_URW_SRW 0x0A
103#define PTE_TYPE_URX_SRX 0x0C
104#define PTE_TYPE_URWX_SRWX0x0E
105#define PTE_TYPE_SR 0x10
106#define PTE_TYPE_SRW 0x12
107#define PTE_TYPE_SRX 0x14
108#define PTE_TYPE_SRWX 0x16
109#define PTE_TYPE_SR_GLOBAL 0x18
110#define PTE_TYPE_SRW_GLOBAL 0x1A
111#define PTE_TYPE_SRX_GLOBAL 0x1C
112#define PTE_TYPE_SRWX_GLOBAL 0x1E
113
114#define PTE_PPN_SHIFT 10
115
116#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
117#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
118#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
119#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
120#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
121#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
122#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
123
124#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
125 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
126 (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
127 ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
128
129#ifdef __riscv
130#ifdef CONFIG_64BIT
131# define MSTATUS_SD MSTATUS64_SD
132# define SSTATUS_SD SSTATUS64_SD
133# define MCAUSE_INT MCAUSE64_INT
134# define MCAUSE_CAUSE MCAUSE64_CAUSE
135# define RISCV_PGLEVEL_BITS 9
136#else
137# define MSTATUS_SD MSTATUS32_SD
138# define SSTATUS_SD SSTATUS32_SD
139# define RISCV_PGLEVEL_BITS 10
140# define MCAUSE_INT MCAUSE32_INT
141# define MCAUSE_CAUSE MCAUSE32_CAUSE
142#endif
143#define RISCV_PGSHIFT 12
144#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
145
146#ifndef __ASSEMBLER__
147
148#ifdef __GNUC__
149
150#define read_csr(reg) ({ unsigned long __tmp; \
151 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
152 __tmp; })
153
154#define write_csr(reg, val) ({ \
155if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
156 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
157else \
158 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
159
160#define swap_csr(reg, val) ({ unsigned long __tmp; \
161if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
162 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
163else \
164 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
165 __tmp; })
166
167#define set_csr(reg, bit) ({ unsigned long __tmp; \
168if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
169 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
170else \
171 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
172 __tmp; })
173
174#define clear_csr(reg, bit) ({ unsigned long __tmp; \
175if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
176 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
177else \
178 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
179 __tmp; })
180
181#define rdtime() read_csr(time)
182#define rdcycle() read_csr(cycle)
183#define rdinstret() read_csr(instret)
184
185#endif
186#endif
187#endif
188#endif
189
