LXR uboot/board/freescale/bsc9132qds/spl

   1/*
   2 * Copyright 2013 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <ns16550.h>
   9#include <asm/io.h>
  10#include <nand.h>
  11#include <linux/compiler.h>
  12#include <asm/fsl_law.h>
  13#include <fsl_ddr_sdram.h>
  14#include <asm/global_data.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18static void sdram_init(void)
  19{
  20        struct ccsr_ddr __iomem *ddr =
  21                (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  22#if CONFIG_DDR_CLK_FREQ == 100000000
  23        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  24        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  25        __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
  26        __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
  27        __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  28
  29        __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
  30        __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
  31        __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
  32        __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
  33        __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
  34        __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
  35        __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
  36        __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
  37        __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
  38
  39        __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
  40        __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
  41        __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  42#elif CONFIG_DDR_CLK_FREQ == 133000000
  43        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  44        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  45        __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
  46        __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
  47        __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  48
  49        __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
  50        __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
  51        __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
  52        __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
  53        __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
  54        __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
  55        __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
  56        __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
  57        __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
  58
  59        __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
  60        __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
  61        __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  62#else
  63        puts("Not a valid DDR Freq Found! Please Reset\n");
  64#endif
  65        asm volatile("sync;isync");
  66        udelay(500);
  67
  68        /* Let the controller go */
  69        out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  70
  71        set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
  72}
  73
  74void board_init_f(ulong bootflag)
  75{
  76        u32 plat_ratio;
  77        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  78
  79        /* initialize selected port with appropriate baud rate */
  80        plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  81        plat_ratio >>= 1;
  82        gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  83
  84        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  85                     gd->bus_clk / 16 / CONFIG_BAUDRATE);
  86
  87        puts("\nNAND boot... ");
  88
  89        /* Initialize the DDR3 */
  90        sdram_init();
  91
  92        /* copy code to RAM and jump to it - this should not return */
  93        /* NOTE - code has to be copied out of NAND buffer before
  94         * other blocks can be read.
  95         */
  96        relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  97}
  98
  99void board_init_r(gd_t *gd, ulong dest_addr)
 100{
 101        nand_boot();
 102}
 103
 104void putc(char c)
 105{
 106        if (c == '\n')
 107                NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 108
 109        NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 110}
 111
 112void puts(const char *str)
 113{
 114        while (*str)
 115                putc(*str++);
 116}
 117