LXR uboot/board/freescale/ls1046aqds/ls1046aqds.c

   1/*
   2 * Copyright 2016 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <fdt_support.h>
  10#include <fsl_ddr_sdram.h>
  11#include <asm/io.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/fsl_serdes.h>
  14#include <asm/arch/ppa.h>
  15#include <asm/arch/fdt.h>
  16#include <asm/arch/mmu.h>
  17#include <asm/arch/soc.h>
  18#include <ahci.h>
  19#include <hwconfig.h>
  20#include <mmc.h>
  21#include <scsi.h>
  22#include <fm_eth.h>
  23#include <fsl_csu.h>
  24#include <fsl_esdhc.h>
  25#include <fsl_ifc.h>
  26#include <fsl_sec.h>
  27#include <spl.h>
  28
  29#include "../common/vid.h"
  30#include "../common/qixis.h"
  31#include "ls1046aqds_qixis.h"
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35enum {
  36        MUX_TYPE_GPIO,
  37};
  38
  39int checkboard(void)
  40{
  41        char buf[64];
  42#ifndef CONFIG_SD_BOOT
  43        u8 sw;
  44#endif
  45
  46        puts("Board: LS1046AQDS, boot from ");
  47
  48#ifdef CONFIG_SD_BOOT
  49        puts("SD\n");
  50#else
  51        sw = QIXIS_READ(brdcfg[0]);
  52        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  53
  54        if (sw < 0x8)
  55                printf("vBank: %d\n", sw);
  56        else if (sw == 0x8)
  57                puts("PromJet\n");
  58        else if (sw == 0x9)
  59                puts("NAND\n");
  60        else if (sw == 0xF)
  61                printf("QSPI\n");
  62        else
  63                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  64#endif
  65
  66        printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  67               QIXIS_READ(id), QIXIS_READ(arch));
  68
  69        printf("FPGA:  v%d (%s), build %d\n",
  70               (int)QIXIS_READ(scver), qixis_read_tag(buf),
  71               (int)qixis_read_minor());
  72
  73        return 0;
  74}
  75
  76bool if_board_diff_clk(void)
  77{
  78        u8 diff_conf = QIXIS_READ(brdcfg[11]);
  79
  80        return diff_conf & 0x40;
  81}
  82
  83unsigned long get_board_sys_clk(void)
  84{
  85        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  86
  87        switch (sysclk_conf & 0x0f) {
  88        case QIXIS_SYSCLK_64:
  89                return 64000000;
  90        case QIXIS_SYSCLK_83:
  91                return 83333333;
  92        case QIXIS_SYSCLK_100:
  93                return 100000000;
  94        case QIXIS_SYSCLK_125:
  95                return 125000000;
  96        case QIXIS_SYSCLK_133:
  97                return 133333333;
  98        case QIXIS_SYSCLK_150:
  99                return 150000000;
 100        case QIXIS_SYSCLK_160:
 101                return 160000000;
 102        case QIXIS_SYSCLK_166:
 103                return 166666666;
 104        }
 105
 106        return 66666666;
 107}
 108
 109unsigned long get_board_ddr_clk(void)
 110{
 111        u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 112
 113        if (if_board_diff_clk())
 114                return get_board_sys_clk();
 115        switch ((ddrclk_conf & 0x30) >> 4) {
 116        case QIXIS_DDRCLK_100:
 117                return 100000000;
 118        case QIXIS_DDRCLK_125:
 119                return 125000000;
 120        case QIXIS_DDRCLK_133:
 121                return 133333333;
 122        }
 123
 124        return 66666666;
 125}
 126
 127#ifdef CONFIG_LPUART
 128u32 get_lpuart_clk(void)
 129{
 130        return gd->bus_clk;
 131}
 132#endif
 133
 134int select_i2c_ch_pca9547(u8 ch)
 135{
 136        int ret;
 137
 138        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 139        if (ret) {
 140                puts("PCA: failed to select proper channel\n");
 141                return ret;
 142        }
 143
 144        return 0;
 145}
 146
 147int dram_init(void)
 148{
 149        /*
 150         * When resuming from deep sleep, the I2C channel may not be
 151         * in the default channel. So, switch to the default channel
 152         * before accessing DDR SPD.
 153         */
 154        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 155        fsl_initdram();
 156#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 157        /* This will break-before-make MMU for DDR */
 158        update_early_mmu_table();
 159#endif
 160
 161        return 0;
 162}
 163
 164int i2c_multiplexer_select_vid_channel(u8 channel)
 165{
 166        return select_i2c_ch_pca9547(channel);
 167}
 168
 169int board_early_init_f(void)
 170{
 171#ifdef CONFIG_HAS_FSL_XHCI_USB
 172        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 173        u32 usb_pwrfault;
 174#endif
 175#ifdef CONFIG_LPUART
 176        u8 uart;
 177#endif
 178
 179#ifdef CONFIG_SYS_I2C_EARLY_INIT
 180        i2c_early_init_f();
 181#endif
 182        fsl_lsch2_early_init_f();
 183
 184#ifdef CONFIG_HAS_FSL_XHCI_USB
 185        out_be32(&scfg->rcwpmuxcr0, 0x3333);
 186        out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 187        usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 188                        SCFG_USBPWRFAULT_USB3_SHIFT) |
 189                        (SCFG_USBPWRFAULT_DEDICATED <<
 190                        SCFG_USBPWRFAULT_USB2_SHIFT) |
 191                        (SCFG_USBPWRFAULT_SHARED <<
 192                        SCFG_USBPWRFAULT_USB1_SHIFT);
 193        out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 194#endif
 195
 196#ifdef CONFIG_LPUART
 197        /* We use lpuart0 as system console */
 198        uart = QIXIS_READ(brdcfg[14]);
 199        uart &= ~CFG_UART_MUX_MASK;
 200        uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 201        QIXIS_WRITE(brdcfg[14], uart);
 202#endif
 203
 204        return 0;
 205}
 206
 207#ifdef CONFIG_FSL_DEEP_SLEEP
 208/* determine if it is a warm boot */
 209bool is_warm_boot(void)
 210{
 211#define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 212        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 213
 214        if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 215                return 1;
 216
 217        return 0;
 218}
 219#endif
 220
 221int config_board_mux(int ctrl_type)
 222{
 223        u8 reg14;
 224
 225        reg14 = QIXIS_READ(brdcfg[14]);
 226
 227        switch (ctrl_type) {
 228        case MUX_TYPE_GPIO:
 229                reg14 = (reg14 & (~0x6)) | 0x2;
 230                break;
 231        default:
 232                puts("Unsupported mux interface type\n");
 233                return -1;
 234        }
 235
 236        QIXIS_WRITE(brdcfg[14], reg14);
 237
 238        return 0;
 239}
 240
 241int config_serdes_mux(void)
 242{
 243        return 0;
 244}
 245
 246#ifdef CONFIG_MISC_INIT_R
 247int misc_init_r(void)
 248{
 249        if (hwconfig("gpio"))
 250                config_board_mux(MUX_TYPE_GPIO);
 251
 252        return 0;
 253}
 254#endif
 255
 256int board_init(void)
 257{
 258        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 259
 260#ifdef CONFIG_SYS_FSL_SERDES
 261        config_serdes_mux();
 262#endif
 263
 264        if (adjust_vdd(0))
 265                printf("Warning: Adjusting core voltage failed.\n");
 266
 267#ifdef CONFIG_FSL_LS_PPA
 268        ppa_init();
 269#endif
 270
 271#ifdef CONFIG_SECURE_BOOT
 272        /*
 273         * In case of Secure Boot, the IBR configures the SMMU
 274         * to allow only Secure transactions.
 275         * SMMU must be reset in bypass mode.
 276         * Set the ClientPD bit and Clear the USFCFG Bit
 277         */
 278        u32 val;
 279        val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 280        out_le32(SMMU_SCR0, val);
 281        val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 282        out_le32(SMMU_NSCR0, val);
 283#endif
 284
 285#ifdef CONFIG_FSL_CAAM
 286        sec_init();
 287#endif
 288
 289        return 0;
 290}
 291
 292#ifdef CONFIG_OF_BOARD_SETUP
 293int ft_board_setup(void *blob, bd_t *bd)
 294{
 295        u64 base[CONFIG_NR_DRAM_BANKS];
 296        u64 size[CONFIG_NR_DRAM_BANKS];
 297        u8 reg;
 298
 299        /* fixup DT for the two DDR banks */
 300        base[0] = gd->bd->bi_dram[0].start;
 301        size[0] = gd->bd->bi_dram[0].size;
 302        base[1] = gd->bd->bi_dram[1].start;
 303        size[1] = gd->bd->bi_dram[1].size;
 304
 305        fdt_fixup_memory_banks(blob, base, size, 2);
 306        ft_cpu_setup(blob, bd);
 307
 308#ifdef CONFIG_SYS_DPAA_FMAN
 309        fdt_fixup_fman_ethernet(blob);
 310        fdt_fixup_board_enet(blob);
 311#endif
 312
 313        reg = QIXIS_READ(brdcfg[0]);
 314        reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 315
 316        /* Disable IFC if QSPI is enabled */
 317        if (reg == 0xF)
 318                do_fixup_by_compat(blob, "fsl,ifc",
 319                                   "status", "disabled", 8 + 1, 1);
 320
 321        return 0;
 322}
 323#endif
 324
 325u8 flash_read8(void *addr)
 326{
 327        return __raw_readb(addr + 1);
 328}
 329
 330void flash_write16(u16 val, void *addr)
 331{
 332        u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 333
 334        __raw_writew(shftval, addr);
 335}
 336
 337u16 flash_read16(void *addr)
 338{
 339        u16 val = __raw_readw(addr);
 340
 341        return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 342}
 343