LXR uboot/board/freescale/m5275evb/m5275evb.c

   1/*
   2 * (C) Copyright 2000-2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
   6 *
   7 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#include <common.h>
  13#include <asm/immap.h>
  14#include <asm/io.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18#define PERIOD          13      /* system bus period in ns */
  19#define SDRAM_TREFI     7800    /* in ns */
  20
  21int checkboard(void)
  22{
  23        puts("Board: ");
  24        puts("Freescale MCF5275 EVB\n");
  25        return 0;
  26};
  27
  28int dram_init(void)
  29{
  30        sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
  31        gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
  32
  33        /* Enable SDRAM */
  34        out_be16(&gpio_reg->par_sdram, 0x3FF);
  35
  36        /* Set up chip select */
  37        out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
  38        out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
  39
  40        /* Set up timing */
  41        out_be32(&sdp->sdcfg1, 0x83711630);
  42        out_be32(&sdp->sdcfg2, 0x46770000);
  43
  44        /* Enable clock */
  45        out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
  46
  47        /* Set precharge */
  48        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  49
  50        /* Dummy write to start SDRAM */
  51        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  52
  53        /* Send LEMR */
  54        setbits_be32(&sdp->sdmr,
  55                MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
  56                MCF_SDRAMC_SDMR_CMD);
  57        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  58
  59        /* Send LMR */
  60        out_be32(&sdp->sdmr, 0x058d0000);
  61        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  62
  63        /* Stop sending commands */
  64        clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  65
  66        /* Set precharge */
  67        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  68        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  69
  70        /* Stop manual precharge, send 2 IREF */
  71        clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  72        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
  73        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  74        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  75
  76
  77        out_be32(&sdp->sdmr, 0x018d0000);
  78        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  79
  80        /* Stop sending commands */
  81        clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  82        clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
  83
  84        /* Turn on auto refresh, lock SDMR */
  85        out_be32(&sdp->sdcr,
  86                MCF_SDRAMC_SDCR_CKE
  87                | MCF_SDRAMC_SDCR_REF
  88                | MCF_SDRAMC_SDCR_MUX(1)
  89                /* 1 added to round up */
  90                | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
  91                | MCF_SDRAMC_SDCR_DQS_OE(0x3));
  92
  93        gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  94
  95        return 0;
  96};
  97
  98int testdram(void)
  99{
 100        /* TODO: XXX XXX XXX */
 101        printf("DRAM test not implemented!\n");
 102
 103        return (0);
 104}
 105