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5
6
7#include <common.h>
8#include <miiphy.h>
9#include <asm/io.h>
10#include <asm/arch/cpu.h>
11#include <asm/arch/soc.h>
12#include <linux/mbus.h>
13
14#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
15#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19
20#define DEV_CS0_BASE 0xe0000000
21#define DEV_CS1_BASE 0xe1000000
22#define DEV_CS2_BASE 0xe2000000
23#define DEV_CS3_BASE 0xe3000000
24
25
26MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = {
27 {0x00001400, 0x7301CC30},
28 {0x00001404, 0x30000820},
29 {0x00001408, 0x5515BAAB},
30 {0x0000140C, 0x38DA3F97},
31 {0x00001410, 0x20100005},
32 {0x00001414, 0x0000F3FF},
33 {0x00001418, 0x00000e00},
34 {0x0000141C, 0x00000672},
35 {0x00001420, 0x00000004},
36 {0x00001424, 0x0000F3FF},
37 {0x00001428, 0x0011A940},
38 {0x0000142C, 0x014C5134},
39 {0x0000147C, 0x0000D771},
40
41 {0x00001494, 0x00010000},
42 {0x0000149C, 0x00000001},
43 {0x000014A0, 0x00000001},
44 {0x000014A8, 0x00000101},
45
46
47 {0x000014C0, 0x192424C9},
48 {0x000014C4, 0xAAA24C9},
49
50
51
52
53
54 {0x000200e8, 0x3FFF0E01},
55 {0x00020184, 0x3FFFFFE0},
56
57 {0x0001504, 0x3FFFFFE1},
58 {0x000150C, 0x00000000},
59 {0x0001514, 0x00000000},
60 {0x000151C, 0x00000000},
61
62 {0x0020220, 0x00000007},
63
64 {0x00001538, 0x0000000B},
65 {0x0000153C, 0x0000000B},
66
67 {0x000015D0, 0x00000670},
68 {0x000015D4, 0x00000044},
69 {0x000015D8, 0x00000018},
70 {0x000015DC, 0x00000000},
71 {0x000015E0, 0x00000001},
72 {0x000015E4, 0x00203c18},
73 {0x000015EC, 0xF800A225},
74
75 {0x0, 0x0}
76};
77
78MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = {
79 {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
80};
81
82extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
83
84
85MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = {
86 { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
87 { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
88 PEX_BUS_DISABLED },
89 0x1f, serdes_change_m_phy
90 }
91};
92
93MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
94{
95
96 return &maxbcm_ddr_modes[0];
97}
98
99MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
100{
101 return &maxbcm_serdes_cfg[0];
102}
103
104int board_early_init_f(void)
105{
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107
108
109
110
111
112
113
114 mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
115 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
116 mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
117 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
118 mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
119 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
120 mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
121 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
122
123 return 0;
124}
125
126int board_init(void)
127{
128
129 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
130
131 return 0;
132}
133
134int checkboard(void)
135{
136 puts("Board: maxBCM\n");
137
138 return 0;
139}
140
141
142int board_phy_config(struct phy_device *phydev)
143{
144
145
146
147
148
149
150 printf("88E6185 Initialized\n");
151 return 0;
152}
153