LXR uboot/board/toradex/colibri_pxa270/colibri

   1/*
   2 * Toradex Colibri PXA270 Support
   3 *
   4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5 * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <dm.h>
  12#include <asm/arch/hardware.h>
  13#include <asm/arch/pxa.h>
  14#include <asm/arch/regs-mmc.h>
  15#include <asm/arch/regs-uart.h>
  16#include <asm/io.h>
  17#include <dm/platdata.h>
  18#include <dm/platform_data/serial_pxa.h>
  19#include <netdev.h>
  20#include <serial.h>
  21#include <usb.h>
  22#include <asm/mach-types.h>
  23#include "../common/tdx-common.h"
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27int board_init(void)
  28{
  29        /* We have RAM, disable cache */
  30        dcache_disable();
  31        icache_disable();
  32
  33        /* arch number of Toradex Colibri PXA270 */
  34        gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
  35
  36        /* adress of boot parameters */
  37        gd->bd->bi_boot_params = 0xa0000100;
  38
  39        return 0;
  40}
  41
  42int checkboard(void)
  43{
  44        puts("Model: Toradex Colibri PXA270\n");
  45
  46        return 0;
  47}
  48
  49#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  50int ft_board_setup(void *blob, bd_t *bd)
  51{
  52        return ft_common_board_setup(blob, bd);
  53}
  54#endif
  55
  56int dram_init(void)
  57{
  58        pxa2xx_dram_init();
  59        gd->ram_size = PHYS_SDRAM_1_SIZE;
  60        return 0;
  61}
  62
  63#ifdef  CONFIG_CMD_USB
  64int board_usb_init(int index, enum usb_init_type init)
  65{
  66        writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  67                ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  68                UHCHR);
  69
  70        writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  71
  72        while (UHCHR & UHCHR_FSBIR)
  73                ;
  74
  75        writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  76        writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  77
  78        /* Clear any OTG Pin Hold */
  79        if (readl(PSSR) & PSSR_OTGPH)
  80                writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  81
  82        writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  83        writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  84
  85        /* Set port power control mask bits, only 3 ports. */
  86        writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  87
  88        /* enable port 2 */
  89        writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  90                UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  91
  92        return 0;
  93}
  94
  95int board_usb_cleanup(int index, enum usb_init_type init)
  96{
  97        return 0;
  98}
  99
 100void usb_board_stop(void)
 101{
 102        writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 103        udelay(11);
 104        writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 105
 106        writel(readl(UHCCOMS) | 1, UHCCOMS);
 107        udelay(10);
 108
 109        writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 110
 111        return;
 112}
 113#endif
 114
 115#ifdef CONFIG_DRIVER_DM9000
 116int board_eth_init(bd_t *bis)
 117{
 118        return dm9000_initialize(bis);
 119}
 120#endif
 121
 122#ifdef  CONFIG_CMD_MMC
 123int board_mmc_init(bd_t *bis)
 124{
 125        pxa_mmc_register(0);
 126        return 0;
 127}
 128#endif
 129
 130static const struct pxa_serial_platdata serial_platdata = {
 131        .base = (struct pxa_uart_regs *)FFUART_BASE,
 132        .port = FFUART_INDEX,
 133        .baudrate = CONFIG_BAUDRATE,
 134};
 135
 136U_BOOT_DEVICE(pxa_serials) = {
 137        .name = "serial_pxa",
 138        .platdata = &serial_platdata,
 139};
 140