uboot/drivers/net/smc91111.c
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   1/*------------------------------------------------------------------------
   2 . smc91111.c
   3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
   4 .
   5 . (C) Copyright 2002
   6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7 . Rolf Offermanns <rof@sysgo.de>
   8 .
   9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  10 .       Developed by Simple Network Magic Corporation (SNMC)
  11 . Copyright (C) 1996 by Erik Stahlman (ES)
  12 .
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 .
  15 . Information contained in this file was obtained from the LAN91C111
  16 . manual from SMC.  To get a copy, if you really want one, you can find
  17 . information under www.smsc.com.
  18 .
  19 .
  20 . "Features" of the SMC chip:
  21 .   Integrated PHY/MAC for 10/100BaseT Operation
  22 .   Supports internal and external MII
  23 .   Integrated 8K packet memory
  24 .   EEPROM interface for configuration
  25 .
  26 . Arguments:
  27 .      io      = for the base address
  28 .      irq     = for the IRQ
  29 .
  30 . author:
  31 .      Erik Stahlman                           ( erik@vt.edu )
  32 .      Daris A Nevil                           ( dnevil@snmc.com )
  33 .
  34 .
  35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  36 .
  37 . Sources:
  38 .    o   SMSC LAN91C111 databook (www.smsc.com)
  39 .    o   smc9194.c by Erik Stahlman
  40 .    o   skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  41 .
  42 . History:
  43 .      06/19/03  Richard Woodruff Made u-boot environment aware and added mac addr checks.
  44 .      10/17/01  Marco Hasewinkel Modify for DNP/1110
  45 .      07/25/01  Woojung Huh      Modify for ADS Bitsy
  46 .      04/25/01  Daris A Nevil    Initial public release through SMSC
  47 .      03/16/01  Daris A Nevil    Modified smc9194.c for use with LAN91C111
  48 ----------------------------------------------------------------------------*/
  49
  50#include <common.h>
  51#include <command.h>
  52#include <config.h>
  53#include <malloc.h>
  54#include "smc91111.h"
  55#include <net.h>
  56
  57/* Use power-down feature of the chip */
  58#define POWER_DOWN      0
  59
  60#define NO_AUTOPROBE
  61
  62#define SMC_DEBUG 0
  63
  64#if SMC_DEBUG > 1
  65static const char version[] =
  66        "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
  67#endif
  68
  69/* Autonegotiation timeout in seconds */
  70#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
  71#define CONFIG_SMC_AUTONEG_TIMEOUT 10
  72#endif
  73
  74/*------------------------------------------------------------------------
  75 .
  76 . Configuration options, for the experienced user to change.
  77 .
  78 -------------------------------------------------------------------------*/
  79
  80/*
  81 . Wait time for memory to be free.  This probably shouldn't be
  82 . tuned that much, as waiting for this means nothing else happens
  83 . in the system
  84*/
  85#define MEMORY_WAIT_TIME 16
  86
  87
  88#if (SMC_DEBUG > 2 )
  89#define PRINTK3(args...) printf(args)
  90#else
  91#define PRINTK3(args...)
  92#endif
  93
  94#if SMC_DEBUG > 1
  95#define PRINTK2(args...) printf(args)
  96#else
  97#define PRINTK2(args...)
  98#endif
  99
 100#ifdef SMC_DEBUG
 101#define PRINTK(args...) printf(args)
 102#else
 103#define PRINTK(args...)
 104#endif
 105
 106
 107/*------------------------------------------------------------------------
 108 .
 109 . The internal workings of the driver.  If you are changing anything
 110 . here with the SMC stuff, you should have the datasheet and know
 111 . what you are doing.
 112 .
 113 -------------------------------------------------------------------------*/
 114
 115/* Memory sizing constant */
 116#define LAN91C111_MEMORY_MULTIPLIER     (1024*2)
 117
 118#ifndef CONFIG_SMC91111_BASE
 119#error "SMC91111 Base address must be passed to initialization funciton"
 120/* #define CONFIG_SMC91111_BASE 0x20000300 */
 121#endif
 122
 123#define SMC_DEV_NAME "SMC91111"
 124#define SMC_PHY_ADDR 0x0000
 125#define SMC_ALLOC_MAX_TRY 5
 126#define SMC_TX_TIMEOUT 30
 127
 128#define SMC_PHY_CLOCK_DELAY 1000
 129
 130#define ETH_ZLEN 60
 131
 132#ifdef  CONFIG_SMC_USE_32_BIT
 133#define USE_32_BIT  1
 134#else
 135#undef USE_32_BIT
 136#endif
 137
 138#ifdef SHARED_RESOURCES
 139extern void swap_to(int device_id);
 140#else
 141# define swap_to(x)
 142#endif
 143
 144#ifndef CONFIG_SMC91111_EXT_PHY
 145static void smc_phy_configure(struct eth_device *dev);
 146#endif /* !CONFIG_SMC91111_EXT_PHY */
 147
 148/*
 149 ------------------------------------------------------------
 150 .
 151 . Internal routines
 152 .
 153 ------------------------------------------------------------
 154*/
 155
 156#ifdef CONFIG_SMC_USE_IOFUNCS
 157/*
 158 * input and output functions
 159 *
 160 * Implemented due to inx,outx macros accessing the device improperly
 161 * and putting the device into an unkown state.
 162 *
 163 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
 164 * could not be free'd (hence the alloc failures), duplicate packets,
 165 * packets being corrupt (shifted) on the wire, etc.  Switching to the
 166 * inx,outx functions fixed this problem.
 167 */
 168
 169static inline word SMC_inw(struct eth_device *dev, dword offset)
 170{
 171        word v;
 172        v = *((volatile word*)(dev->iobase + offset));
 173        barrier(); *(volatile u32*)(0xc0000000);
 174        return v;
 175}
 176
 177static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
 178{
 179        *((volatile word*)(dev->iobase + offset)) = value;
 180        barrier(); *(volatile u32*)(0xc0000000);
 181}
 182
 183static inline byte SMC_inb(struct eth_device *dev, dword offset)
 184{
 185        word  _w;
 186
 187        _w = SMC_inw(dev, offset & ~((dword)1));
 188        return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
 189}
 190
 191static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
 192{
 193        word  _w;
 194
 195        _w = SMC_inw(dev, offset & ~((dword)1));
 196        if (offset & 1)
 197                *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
 198                        (value<<8) | (_w & 0x00ff);
 199        else
 200                *((volatile word*)(dev->iobase + offset)) =
 201                        value | (_w & 0xff00);
 202}
 203
 204static inline void SMC_insw(struct eth_device *dev, dword offset,
 205        volatile uchar* buf, dword len)
 206{
 207        volatile word *p = (volatile word *)buf;
 208
 209        while (len-- > 0) {
 210                *p++ = SMC_inw(dev, offset);
 211                barrier();
 212                *((volatile u32*)(0xc0000000));
 213        }
 214}
 215
 216static inline void SMC_outsw(struct eth_device *dev, dword offset,
 217        uchar* buf, dword len)
 218{
 219        volatile word *p = (volatile word *)buf;
 220
 221        while (len-- > 0) {
 222                SMC_outw(dev, *p++, offset);
 223                barrier();
 224                *(volatile u32*)(0xc0000000);
 225        }
 226}
 227#endif  /* CONFIG_SMC_USE_IOFUNCS */
 228
 229/*
 230 . A rather simple routine to print out a packet for debugging purposes.
 231*/
 232#if SMC_DEBUG > 2
 233static void print_packet( byte *, int );
 234#endif
 235
 236#define tx_done(dev) 1
 237
 238static int poll4int (struct eth_device *dev, byte mask, int timeout)
 239{
 240        int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
 241        int is_timeout = 0;
 242        word old_bank = SMC_inw (dev, BSR_REG);
 243
 244        PRINTK2 ("Polling...\n");
 245        SMC_SELECT_BANK (dev, 2);
 246        while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
 247                if (get_timer (0) >= tmo) {
 248                        is_timeout = 1;
 249                        break;
 250                }
 251        }
 252
 253        /* restore old bank selection */
 254        SMC_SELECT_BANK (dev, old_bank);
 255
 256        if (is_timeout)
 257                return 1;
 258        else
 259                return 0;
 260}
 261
 262/* Only one release command at a time, please */
 263static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
 264{
 265        int count = 0;
 266
 267        /* assume bank 2 selected */
 268        while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
 269                udelay (1);     /* Wait until not busy */
 270                if (++count > 200)
 271                        break;
 272        }
 273}
 274
 275/*
 276 . Function: smc_reset( void )
 277 . Purpose:
 278 .      This sets the SMC91111 chip to its normal state, hopefully from whatever
 279 .      mess that any other DOS driver has put it in.
 280 .
 281 . Maybe I should reset more registers to defaults in here?  SOFTRST  should
 282 . do that for me.
 283 .
 284 . Method:
 285 .      1.  send a SOFT RESET
 286 .      2.  wait for it to finish
 287 .      3.  enable autorelease mode
 288 .      4.  reset the memory management unit
 289 .      5.  clear all interrupts
 290 .
 291*/
 292static void smc_reset (struct eth_device *dev)
 293{
 294        PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
 295
 296        /* This resets the registers mostly to defaults, but doesn't
 297           affect EEPROM.  That seems unnecessary */
 298        SMC_SELECT_BANK (dev, 0);
 299        SMC_outw (dev, RCR_SOFTRST, RCR_REG);
 300
 301        /* Setup the Configuration Register */
 302        /* This is necessary because the CONFIG_REG is not affected */
 303        /* by a soft reset */
 304
 305        SMC_SELECT_BANK (dev, 1);
 306#if defined(CONFIG_SMC91111_EXT_PHY)
 307        SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
 308#else
 309        SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
 310#endif
 311
 312
 313        /* Release from possible power-down state */
 314        /* Configuration register is not affected by Soft Reset */
 315        SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
 316                CONFIG_REG);
 317
 318        SMC_SELECT_BANK (dev, 0);
 319
 320        /* this should pause enough for the chip to be happy */
 321        udelay (10);
 322
 323        /* Disable transmit and receive functionality */
 324        SMC_outw (dev, RCR_CLEAR, RCR_REG);
 325        SMC_outw (dev, TCR_CLEAR, TCR_REG);
 326
 327        /* set the control register */
 328        SMC_SELECT_BANK (dev, 1);
 329        SMC_outw (dev, CTL_DEFAULT, CTL_REG);
 330
 331        /* Reset the MMU */
 332        SMC_SELECT_BANK (dev, 2);
 333        smc_wait_mmu_release_complete (dev);
 334        SMC_outw (dev, MC_RESET, MMU_CMD_REG);
 335        while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
 336                udelay (1);     /* Wait until not busy */
 337
 338        /* Note:  It doesn't seem that waiting for the MMU busy is needed here,
 339           but this is a place where future chipsets _COULD_ break.  Be wary
 340           of issuing another MMU command right after this */
 341
 342        /* Disable all interrupts */
 343        SMC_outb (dev, 0, IM_REG);
 344}
 345
 346/*
 347 . Function: smc_enable
 348 . Purpose: let the chip talk to the outside work
 349 . Method:
 350 .      1.  Enable the transmitter
 351 .      2.  Enable the receiver
 352 .      3.  Enable interrupts
 353*/
 354static void smc_enable(struct eth_device *dev)
 355{
 356        PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
 357        SMC_SELECT_BANK( dev, 0 );
 358        /* see the header file for options in TCR/RCR DEFAULT*/
 359        SMC_outw( dev, TCR_DEFAULT, TCR_REG );
 360        SMC_outw( dev, RCR_DEFAULT, RCR_REG );
 361
 362        /* clear MII_DIS */
 363/*      smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
 364}
 365
 366/*
 367 . Function: smc_halt
 368 . Purpose:  closes down the SMC91xxx chip.
 369 . Method:
 370 .      1. zero the interrupt mask
 371 .      2. clear the enable receive flag
 372 .      3. clear the enable xmit flags
 373 .
 374 . TODO:
 375 .   (1) maybe utilize power down mode.
 376 .      Why not yet?  Because while the chip will go into power down mode,
 377 .      the manual says that it will wake up in response to any I/O requests
 378 .      in the register space.   Empirical results do not show this working.
 379*/
 380static void smc_halt(struct eth_device *dev)
 381{
 382        PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
 383
 384        /* no more interrupts for me */
 385        SMC_SELECT_BANK( dev, 2 );
 386        SMC_outb( dev, 0, IM_REG );
 387
 388        /* and tell the card to stay away from that nasty outside world */
 389        SMC_SELECT_BANK( dev, 0 );
 390        SMC_outb( dev, RCR_CLEAR, RCR_REG );
 391        SMC_outb( dev, TCR_CLEAR, TCR_REG );
 392
 393        swap_to(FLASH);
 394}
 395
 396
 397/*
 398 . Function:  smc_send(struct net_device * )
 399 . Purpose:
 400 .      This sends the actual packet to the SMC9xxx chip.
 401 .
 402 . Algorithm:
 403 .      First, see if a saved_skb is available.
 404 .              ( this should NOT be called if there is no 'saved_skb'
 405 .      Now, find the packet number that the chip allocated
 406 .      Point the data pointers at it in memory
 407 .      Set the length word in the chip's memory
 408 .      Dump the packet to chip memory
 409 .      Check if a last byte is needed ( odd length packet )
 410 .              if so, set the control flag right
 411 .      Tell the card to send it
 412 .      Enable the transmit interrupt, so I know if it failed
 413 .      Free the kernel data if I actually sent it.
 414*/
 415static int smc_send(struct eth_device *dev, void *packet, int packet_length)
 416{
 417        byte packet_no;
 418        byte *buf;
 419        int length;
 420        int numPages;
 421        int try = 0;
 422        int time_out;
 423        byte status;
 424        byte saved_pnr;
 425        word saved_ptr;
 426
 427        /* save PTR and PNR registers before manipulation */
 428        SMC_SELECT_BANK (dev, 2);
 429        saved_pnr = SMC_inb( dev, PN_REG );
 430        saved_ptr = SMC_inw( dev, PTR_REG );
 431
 432        PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
 433
 434        length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
 435
 436        /* allocate memory
 437         ** The MMU wants the number of pages to be the number of 256 bytes
 438         ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
 439         **
 440         ** The 91C111 ignores the size bits, but the code is left intact
 441         ** for backwards and future compatibility.
 442         **
 443         ** Pkt size for allocating is data length +6 (for additional status
 444         ** words, length and ctl!)
 445         **
 446         ** If odd size then last byte is included in this header.
 447         */
 448        numPages = ((length & 0xfffe) + 6);
 449        numPages >>= 8;         /* Divide by 256 */
 450
 451        if (numPages > 7) {
 452                printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
 453                return 0;
 454        }
 455
 456        /* now, try to allocate the memory */
 457        SMC_SELECT_BANK (dev, 2);
 458        SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
 459
 460        /* FIXME: the ALLOC_INT bit never gets set *
 461         * so the following will always give a     *
 462         * memory allocation error.                *
 463         * same code works in armboot though       *
 464         * -ro
 465         */
 466
 467again:
 468        try++;
 469        time_out = MEMORY_WAIT_TIME;
 470        do {
 471                status = SMC_inb (dev, SMC91111_INT_REG);
 472                if (status & IM_ALLOC_INT) {
 473                        /* acknowledge the interrupt */
 474                        SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
 475                        break;
 476                }
 477        } while (--time_out);
 478
 479        if (!time_out) {
 480                PRINTK2 ("%s: memory allocation, try %d failed ...\n",
 481                         SMC_DEV_NAME, try);
 482                if (try < SMC_ALLOC_MAX_TRY)
 483                        goto again;
 484                else
 485                        return 0;
 486        }
 487
 488        PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
 489                 SMC_DEV_NAME, try);
 490
 491        buf = (byte *) packet;
 492
 493        /* If I get here, I _know_ there is a packet slot waiting for me */
 494        packet_no = SMC_inb (dev, AR_REG);
 495        if (packet_no & AR_FAILED) {
 496                /* or isn't there?  BAD CHIP! */
 497                printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
 498                return 0;
 499        }
 500
 501        /* we have a packet address, so tell the card to use it */
 502        SMC_outb (dev, packet_no, PN_REG);
 503
 504        /* do not write new ptr value if Write data fifo not empty */
 505        while ( saved_ptr & PTR_NOTEMPTY )
 506                printf ("Write data fifo not empty!\n");
 507
 508        /* point to the beginning of the packet */
 509        SMC_outw (dev, PTR_AUTOINC, PTR_REG);
 510
 511        PRINTK3 ("%s: Trying to xmit packet of length %x\n",
 512                 SMC_DEV_NAME, length);
 513
 514#if SMC_DEBUG > 2
 515        printf ("Transmitting Packet\n");
 516        print_packet (buf, length);
 517#endif
 518
 519        /* send the packet length ( +6 for status, length and ctl byte )
 520           and the status word ( set to zeros ) */
 521#ifdef USE_32_BIT
 522        SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
 523#else
 524        SMC_outw (dev, 0, SMC91111_DATA_REG);
 525        /* send the packet length ( +6 for status words, length, and ctl */
 526        SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
 527#endif
 528
 529        /* send the actual data
 530           . I _think_ it's faster to send the longs first, and then
 531           . mop up by sending the last word.  It depends heavily
 532           . on alignment, at least on the 486.  Maybe it would be
 533           . a good idea to check which is optimal?  But that could take
 534           . almost as much time as is saved?
 535         */
 536#ifdef USE_32_BIT
 537        SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
 538        if (length & 0x2)
 539                SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
 540                          SMC91111_DATA_REG);
 541#else
 542        SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
 543#endif /* USE_32_BIT */
 544
 545        /* Send the last byte, if there is one.   */
 546        if ((length & 1) == 0) {
 547                SMC_outw (dev, 0, SMC91111_DATA_REG);
 548        } else {
 549                SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
 550        }
 551
 552        /* and let the chipset deal with it */
 553        SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
 554
 555        /* poll for TX INT */
 556        /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
 557        /* poll for TX_EMPTY INT - autorelease enabled */
 558        if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
 559                /* sending failed */
 560                PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
 561
 562                /* release packet */
 563                /* no need to release, MMU does that now */
 564
 565                /* wait for MMU getting ready (low) */
 566                while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
 567                        udelay (10);
 568                }
 569
 570                PRINTK2 ("MMU ready\n");
 571
 572
 573                return 0;
 574        } else {
 575                /* ack. int */
 576                SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
 577                /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
 578                PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
 579                         length);
 580
 581                /* release packet */
 582                /* no need to release, MMU does that now */
 583
 584                /* wait for MMU getting ready (low) */
 585                while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
 586                        udelay (10);
 587                }
 588
 589                PRINTK2 ("MMU ready\n");
 590
 591
 592        }
 593
 594        /* restore previously saved registers */
 595        SMC_outb( dev, saved_pnr, PN_REG );
 596        SMC_outw( dev, saved_ptr, PTR_REG );
 597
 598        return length;
 599}
 600
 601static int smc_write_hwaddr(struct eth_device *dev)
 602{
 603        int i;
 604
 605        swap_to(ETHERNET);
 606        SMC_SELECT_BANK (dev, 1);
 607#ifdef USE_32_BIT
 608        for (i = 0; i < 6; i += 2) {
 609                word address;
 610
 611                address = dev->enetaddr[i + 1] << 8;
 612                address |= dev->enetaddr[i];
 613                SMC_outw(dev, address, (ADDR0_REG + i));
 614        }
 615#else
 616        for (i = 0; i < 6; i++)
 617                SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
 618#endif
 619        swap_to(FLASH);
 620        return 0;
 621}
 622
 623/*
 624 * Open and Initialize the board
 625 *
 626 * Set up everything, reset the card, etc ..
 627 *
 628 */
 629static int smc_init(struct eth_device *dev, bd_t *bd)
 630{
 631        swap_to(ETHERNET);
 632
 633        PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
 634
 635        /* reset the hardware */
 636        smc_reset (dev);
 637        smc_enable (dev);
 638
 639        /* Configure the PHY */
 640#ifndef CONFIG_SMC91111_EXT_PHY
 641        smc_phy_configure (dev);
 642#endif
 643
 644        /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
 645/*      SMC_SELECT_BANK(dev, 0); */
 646/*      SMC_outw(dev, 0, RPC_REG); */
 647
 648        printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
 649
 650        return 0;
 651}
 652
 653/*-------------------------------------------------------------
 654 .
 655 . smc_rcv -  receive a packet from the card
 656 .
 657 . There is ( at least ) a packet waiting to be read from
 658 . chip-memory.
 659 .
 660 . o Read the status
 661 . o If an error, record it
 662 . o otherwise, read in the packet
 663 --------------------------------------------------------------
 664*/
 665static int smc_rcv(struct eth_device *dev)
 666{
 667        int     packet_number;
 668        word    status;
 669        word    packet_length;
 670        int     is_error = 0;
 671#ifdef USE_32_BIT
 672        dword stat_len;
 673#endif
 674        byte saved_pnr;
 675        word saved_ptr;
 676
 677        SMC_SELECT_BANK(dev, 2);
 678        /* save PTR and PTR registers */
 679        saved_pnr = SMC_inb( dev, PN_REG );
 680        saved_ptr = SMC_inw( dev, PTR_REG );
 681
 682        packet_number = SMC_inw( dev, RXFIFO_REG );
 683
 684        if ( packet_number & RXFIFO_REMPTY ) {
 685
 686                return 0;
 687        }
 688
 689        PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
 690        /*  start reading from the start of the packet */
 691        SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
 692
 693        /* First two words are status and packet_length */
 694#ifdef USE_32_BIT
 695        stat_len = SMC_inl(dev, SMC91111_DATA_REG);
 696        status = stat_len & 0xffff;
 697        packet_length = stat_len >> 16;
 698#else
 699        status          = SMC_inw( dev, SMC91111_DATA_REG );
 700        packet_length   = SMC_inw( dev, SMC91111_DATA_REG );
 701#endif
 702
 703        packet_length &= 0x07ff;  /* mask off top bits */
 704
 705        PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
 706
 707        if ( !(status & RS_ERRORS ) ){
 708                /* Adjust for having already read the first two words */
 709                packet_length -= 4; /*4; */
 710
 711
 712                /* set odd length for bug in LAN91C111, */
 713                /* which never sets RS_ODDFRAME */
 714                /* TODO ? */
 715
 716
 717#ifdef USE_32_BIT
 718                PRINTK3(" Reading %d dwords (and %d bytes)\n",
 719                        packet_length >> 2, packet_length & 3 );
 720                /* QUESTION:  Like in the TX routine, do I want
 721                   to send the DWORDs or the bytes first, or some
 722                   mixture.  A mixture might improve already slow PIO
 723                   performance  */
 724                SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
 725                         packet_length >> 2);
 726                /* read the left over bytes */
 727                if (packet_length & 3) {
 728                        int i;
 729
 730                        byte *tail = (byte *)(net_rx_packets[0] +
 731                                (packet_length & ~3));
 732                        dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
 733                        for (i=0; i<(packet_length & 3); i++)
 734                                *tail++ = (byte) (leftover >> (8*i)) & 0xff;
 735                }
 736#else
 737                PRINTK3(" Reading %d words and %d byte(s)\n",
 738                        (packet_length >> 1 ), packet_length & 1 );
 739                SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
 740                         packet_length >> 1);
 741
 742#endif /* USE_32_BIT */
 743
 744#if     SMC_DEBUG > 2
 745                printf("Receiving Packet\n");
 746                print_packet(net_rx_packets[0], packet_length);
 747#endif
 748        } else {
 749                /* error ... */
 750                /* TODO ? */
 751                is_error = 1;
 752        }
 753
 754        while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
 755                udelay(1); /* Wait until not busy */
 756
 757        /*  error or good, tell the card to get rid of this packet */
 758        SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
 759
 760        while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
 761                udelay(1); /* Wait until not busy */
 762
 763        /* restore saved registers */
 764        SMC_outb( dev, saved_pnr, PN_REG );
 765        SMC_outw( dev, saved_ptr, PTR_REG );
 766
 767        if (!is_error) {
 768                /* Pass the packet up to the protocol layers. */
 769                net_process_received_packet(net_rx_packets[0], packet_length);
 770                return packet_length;
 771        } else {
 772                return 0;
 773        }
 774
 775}
 776
 777
 778#if 0
 779/*------------------------------------------------------------
 780 . Modify a bit in the LAN91C111 register set
 781 .-------------------------------------------------------------*/
 782static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
 783        unsigned int bit, int val)
 784{
 785        word regval;
 786
 787        SMC_SELECT_BANK( dev, bank );
 788
 789        regval = SMC_inw( dev, reg );
 790        if (val)
 791                regval |= bit;
 792        else
 793                regval &= ~bit;
 794
 795        SMC_outw( dev, regval, 0 );
 796        return(regval);
 797}
 798
 799
 800/*------------------------------------------------------------
 801 . Retrieve a bit in the LAN91C111 register set
 802 .-------------------------------------------------------------*/
 803static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
 804{
 805        SMC_SELECT_BANK( dev, bank );
 806        if ( SMC_inw( dev, reg ) & bit)
 807                return(1);
 808        else
 809                return(0);
 810}
 811
 812
 813/*------------------------------------------------------------
 814 . Modify a LAN91C111 register (word access only)
 815 .-------------------------------------------------------------*/
 816static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
 817{
 818        SMC_SELECT_BANK( dev, bank );
 819        SMC_outw( dev, val, reg );
 820}
 821
 822
 823/*------------------------------------------------------------
 824 . Retrieve a LAN91C111 register (word access only)
 825 .-------------------------------------------------------------*/
 826static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
 827{
 828        SMC_SELECT_BANK( dev, bank );
 829        return(SMC_inw( dev, reg ));
 830}
 831
 832#endif /* 0 */
 833
 834/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
 835
 836#if (SMC_DEBUG > 2 )
 837
 838/*------------------------------------------------------------
 839 . Debugging function for viewing MII Management serial bitstream
 840 .-------------------------------------------------------------*/
 841static void smc_dump_mii_stream (byte * bits, int size)
 842{
 843        int i;
 844
 845        printf ("BIT#:");
 846        for (i = 0; i < size; ++i) {
 847                printf ("%d", i % 10);
 848        }
 849
 850        printf ("\nMDOE:");
 851        for (i = 0; i < size; ++i) {
 852                if (bits[i] & MII_MDOE)
 853                        printf ("1");
 854                else
 855                        printf ("0");
 856        }
 857
 858        printf ("\nMDO :");
 859        for (i = 0; i < size; ++i) {
 860                if (bits[i] & MII_MDO)
 861                        printf ("1");
 862                else
 863                        printf ("0");
 864        }
 865
 866        printf ("\nMDI :");
 867        for (i = 0; i < size; ++i) {
 868                if (bits[i] & MII_MDI)
 869                        printf ("1");
 870                else
 871                        printf ("0");
 872        }
 873
 874        printf ("\n");
 875}
 876#endif
 877
 878/*------------------------------------------------------------
 879 . Reads a register from the MII Management serial interface
 880 .-------------------------------------------------------------*/
 881#ifndef CONFIG_SMC91111_EXT_PHY
 882static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
 883{
 884        int oldBank;
 885        int i;
 886        byte mask;
 887        word mii_reg;
 888        byte bits[64];
 889        int clk_idx = 0;
 890        int input_idx;
 891        word phydata;
 892        byte phyaddr = SMC_PHY_ADDR;
 893
 894        /* 32 consecutive ones on MDO to establish sync */
 895        for (i = 0; i < 32; ++i)
 896                bits[clk_idx++] = MII_MDOE | MII_MDO;
 897
 898        /* Start code <01> */
 899        bits[clk_idx++] = MII_MDOE;
 900        bits[clk_idx++] = MII_MDOE | MII_MDO;
 901
 902        /* Read command <10> */
 903        bits[clk_idx++] = MII_MDOE | MII_MDO;
 904        bits[clk_idx++] = MII_MDOE;
 905
 906        /* Output the PHY address, msb first */
 907        mask = (byte) 0x10;
 908        for (i = 0; i < 5; ++i) {
 909                if (phyaddr & mask)
 910                        bits[clk_idx++] = MII_MDOE | MII_MDO;
 911                else
 912                        bits[clk_idx++] = MII_MDOE;
 913
 914                /* Shift to next lowest bit */
 915                mask >>= 1;
 916        }
 917
 918        /* Output the phy register number, msb first */
 919        mask = (byte) 0x10;
 920        for (i = 0; i < 5; ++i) {
 921                if (phyreg & mask)
 922                        bits[clk_idx++] = MII_MDOE | MII_MDO;
 923                else
 924                        bits[clk_idx++] = MII_MDOE;
 925
 926                /* Shift to next lowest bit */
 927                mask >>= 1;
 928        }
 929
 930        /* Tristate and turnaround (2 bit times) */
 931        bits[clk_idx++] = 0;
 932        /*bits[clk_idx++] = 0; */
 933
 934        /* Input starts at this bit time */
 935        input_idx = clk_idx;
 936
 937        /* Will input 16 bits */
 938        for (i = 0; i < 16; ++i)
 939                bits[clk_idx++] = 0;
 940
 941        /* Final clock bit */
 942        bits[clk_idx++] = 0;
 943
 944        /* Save the current bank */
 945        oldBank = SMC_inw (dev, BANK_SELECT);
 946
 947        /* Select bank 3 */
 948        SMC_SELECT_BANK (dev, 3);
 949
 950        /* Get the current MII register value */
 951        mii_reg = SMC_inw (dev, MII_REG);
 952
 953        /* Turn off all MII Interface bits */
 954        mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
 955
 956        /* Clock all 64 cycles */
 957        for (i = 0; i < sizeof bits; ++i) {
 958                /* Clock Low - output data */
 959                SMC_outw (dev, mii_reg | bits[i], MII_REG);
 960                udelay (SMC_PHY_CLOCK_DELAY);
 961
 962
 963                /* Clock Hi - input data */
 964                SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
 965                udelay (SMC_PHY_CLOCK_DELAY);
 966                bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
 967        }
 968
 969        /* Return to idle state */
 970        /* Set clock to low, data to low, and output tristated */
 971        SMC_outw (dev, mii_reg, MII_REG);
 972        udelay (SMC_PHY_CLOCK_DELAY);
 973
 974        /* Restore original bank select */
 975        SMC_SELECT_BANK (dev, oldBank);
 976
 977        /* Recover input data */
 978        phydata = 0;
 979        for (i = 0; i < 16; ++i) {
 980                phydata <<= 1;
 981
 982                if (bits[input_idx++] & MII_MDI)
 983                        phydata |= 0x0001;
 984        }
 985
 986#if (SMC_DEBUG > 2 )
 987        printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
 988                phyaddr, phyreg, phydata);
 989        smc_dump_mii_stream (bits, sizeof bits);
 990#endif
 991
 992        return (phydata);
 993}
 994
 995
 996/*------------------------------------------------------------
 997 . Writes a register to the MII Management serial interface
 998 .-------------------------------------------------------------*/
 999static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1000        word phydata)
1001{
1002        int oldBank;
1003        int i;
1004        word mask;
1005        word mii_reg;
1006        byte bits[65];
1007        int clk_idx = 0;
1008        byte phyaddr = SMC_PHY_ADDR;
1009
1010        /* 32 consecutive ones on MDO to establish sync */
1011        for (i = 0; i < 32; ++i)
1012                bits[clk_idx++] = MII_MDOE | MII_MDO;
1013
1014        /* Start code <01> */
1015        bits[clk_idx++] = MII_MDOE;
1016        bits[clk_idx++] = MII_MDOE | MII_MDO;
1017
1018        /* Write command <01> */
1019        bits[clk_idx++] = MII_MDOE;
1020        bits[clk_idx++] = MII_MDOE | MII_MDO;
1021
1022        /* Output the PHY address, msb first */
1023        mask = (byte) 0x10;
1024        for (i = 0; i < 5; ++i) {
1025                if (phyaddr & mask)
1026                        bits[clk_idx++] = MII_MDOE | MII_MDO;
1027                else
1028                        bits[clk_idx++] = MII_MDOE;
1029
1030                /* Shift to next lowest bit */
1031                mask >>= 1;
1032        }
1033
1034        /* Output the phy register number, msb first */
1035        mask = (byte) 0x10;
1036        for (i = 0; i < 5; ++i) {
1037                if (phyreg & mask)
1038                        bits[clk_idx++] = MII_MDOE | MII_MDO;
1039                else
1040                        bits[clk_idx++] = MII_MDOE;
1041
1042                /* Shift to next lowest bit */
1043                mask >>= 1;
1044        }
1045
1046        /* Tristate and turnaround (2 bit times) */
1047        bits[clk_idx++] = 0;
1048        bits[clk_idx++] = 0;
1049
1050        /* Write out 16 bits of data, msb first */
1051        mask = 0x8000;
1052        for (i = 0; i < 16; ++i) {
1053                if (phydata & mask)
1054                        bits[clk_idx++] = MII_MDOE | MII_MDO;
1055                else
1056                        bits[clk_idx++] = MII_MDOE;
1057
1058                /* Shift to next lowest bit */
1059                mask >>= 1;
1060        }
1061
1062        /* Final clock bit (tristate) */
1063        bits[clk_idx++] = 0;
1064
1065        /* Save the current bank */
1066        oldBank = SMC_inw (dev, BANK_SELECT);
1067
1068        /* Select bank 3 */
1069        SMC_SELECT_BANK (dev, 3);
1070
1071        /* Get the current MII register value */
1072        mii_reg = SMC_inw (dev, MII_REG);
1073
1074        /* Turn off all MII Interface bits */
1075        mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1076
1077        /* Clock all cycles */
1078        for (i = 0; i < sizeof bits; ++i) {
1079                /* Clock Low - output data */
1080                SMC_outw (dev, mii_reg | bits[i], MII_REG);
1081                udelay (SMC_PHY_CLOCK_DELAY);
1082
1083
1084                /* Clock Hi - input data */
1085                SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1086                udelay (SMC_PHY_CLOCK_DELAY);
1087                bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1088        }
1089
1090        /* Return to idle state */
1091        /* Set clock to low, data to low, and output tristated */
1092        SMC_outw (dev, mii_reg, MII_REG);
1093        udelay (SMC_PHY_CLOCK_DELAY);
1094
1095        /* Restore original bank select */
1096        SMC_SELECT_BANK (dev, oldBank);
1097
1098#if (SMC_DEBUG > 2 )
1099        printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1100                phyaddr, phyreg, phydata);
1101        smc_dump_mii_stream (bits, sizeof bits);
1102#endif
1103}
1104#endif /* !CONFIG_SMC91111_EXT_PHY */
1105
1106
1107/*------------------------------------------------------------
1108 . Configures the specified PHY using Autonegotiation. Calls
1109 . smc_phy_fixed() if the user has requested a certain config.
1110 .-------------------------------------------------------------*/
1111#ifndef CONFIG_SMC91111_EXT_PHY
1112static void smc_phy_configure (struct eth_device *dev)
1113{
1114        int timeout;
1115        word my_phy_caps;       /* My PHY capabilities */
1116        word my_ad_caps;        /* My Advertised capabilities */
1117        word status = 0;        /*;my status = 0 */
1118
1119        PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1120
1121        /* Reset the PHY, setting all other bits to zero */
1122        smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
1123
1124        /* Wait for the reset to complete, or time out */
1125        timeout = 6;            /* Wait up to 3 seconds */
1126        while (timeout--) {
1127                if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
1128                      & PHY_CNTL_RST)) {
1129                        /* reset complete */
1130                        break;
1131                }
1132
1133                mdelay(500);    /* wait 500 millisecs */
1134        }
1135
1136        if (timeout < 1) {
1137                printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1138                goto smc_phy_configure_exit;
1139        }
1140
1141        /* Read PHY Register 18, Status Output */
1142        /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1143
1144        /* Enable PHY Interrupts (for register 18) */
1145        /* Interrupts listed here are disabled */
1146        smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
1147
1148        /* Configure the Receive/Phy Control register */
1149        SMC_SELECT_BANK (dev, 0);
1150        SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1151
1152        /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1153        my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
1154        my_ad_caps = PHY_AD_CSMA;       /* I am CSMA capable */
1155
1156        if (my_phy_caps & PHY_STAT_CAP_T4)
1157                my_ad_caps |= PHY_AD_T4;
1158
1159        if (my_phy_caps & PHY_STAT_CAP_TXF)
1160                my_ad_caps |= PHY_AD_TX_FDX;
1161
1162        if (my_phy_caps & PHY_STAT_CAP_TXH)
1163                my_ad_caps |= PHY_AD_TX_HDX;
1164
1165        if (my_phy_caps & PHY_STAT_CAP_TF)
1166                my_ad_caps |= PHY_AD_10_FDX;
1167
1168        if (my_phy_caps & PHY_STAT_CAP_TH)
1169                my_ad_caps |= PHY_AD_10_HDX;
1170
1171        /* Update our Auto-Neg Advertisement Register */
1172        smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
1173
1174        /* Read the register back.  Without this, it appears that when */
1175        /* auto-negotiation is restarted, sometimes it isn't ready and */
1176        /* the link does not come up. */
1177        smc_read_phy_register(dev, PHY_AD_REG);
1178
1179        PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1180        PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1181
1182        /* Restart auto-negotiation process in order to advertise my caps */
1183        smc_write_phy_register (dev, PHY_CNTL_REG,
1184                                PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1185
1186        /* Wait for the auto-negotiation to complete.  This may take from */
1187        /* 2 to 3 seconds. */
1188        /* Wait for the reset to complete, or time out */
1189        timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1190        while (timeout--) {
1191
1192                status = smc_read_phy_register (dev, PHY_STAT_REG);
1193                if (status & PHY_STAT_ANEG_ACK) {
1194                        /* auto-negotiate complete */
1195                        break;
1196                }
1197
1198                mdelay(500);    /* wait 500 millisecs */
1199
1200                /* Restart auto-negotiation if remote fault */
1201                if (status & PHY_STAT_REM_FLT) {
1202                        printf ("%s: PHY remote fault detected\n",
1203                                SMC_DEV_NAME);
1204
1205                        /* Restart auto-negotiation */
1206                        printf ("%s: PHY restarting auto-negotiation\n",
1207                                SMC_DEV_NAME);
1208                        smc_write_phy_register (dev, PHY_CNTL_REG,
1209                                                PHY_CNTL_ANEG_EN |
1210                                                PHY_CNTL_ANEG_RST |
1211                                                PHY_CNTL_SPEED |
1212                                                PHY_CNTL_DPLX);
1213                }
1214        }
1215
1216        if (timeout < 1) {
1217                printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1218        }
1219
1220        /* Fail if we detected an auto-negotiate remote fault */
1221        if (status & PHY_STAT_REM_FLT) {
1222                printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1223        }
1224
1225        /* Re-Configure the Receive/Phy Control register */
1226        SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1227
1228smc_phy_configure_exit: ;
1229
1230}
1231#endif /* !CONFIG_SMC91111_EXT_PHY */
1232
1233
1234#if SMC_DEBUG > 2
1235static void print_packet( byte * buf, int length )
1236{
1237        int i;
1238        int remainder;
1239        int lines;
1240
1241        printf("Packet of length %d \n", length );
1242
1243#if SMC_DEBUG > 3
1244        lines = length / 16;
1245        remainder = length % 16;
1246
1247        for ( i = 0; i < lines ; i ++ ) {
1248                int cur;
1249
1250                for ( cur = 0; cur < 8; cur ++ ) {
1251                        byte a, b;
1252
1253                        a = *(buf ++ );
1254                        b = *(buf ++ );
1255                        printf("%02x%02x ", a, b );
1256                }
1257                printf("\n");
1258        }
1259        for ( i = 0; i < remainder/2 ; i++ ) {
1260                byte a, b;
1261
1262                a = *(buf ++ );
1263                b = *(buf ++ );
1264                printf("%02x%02x ", a, b );
1265        }
1266        printf("\n");
1267#endif
1268}
1269#endif
1270
1271int smc91111_initialize(u8 dev_num, int base_addr)
1272{
1273        struct smc91111_priv *priv;
1274        struct eth_device *dev;
1275        int i;
1276
1277        priv = malloc(sizeof(*priv));
1278        if (!priv)
1279                return 0;
1280        dev = malloc(sizeof(*dev));
1281        if (!dev) {
1282                free(priv);
1283                return 0;
1284        }
1285
1286        memset(dev, 0, sizeof(*dev));
1287        priv->dev_num = dev_num;
1288        dev->priv = priv;
1289        dev->iobase = base_addr;
1290
1291        swap_to(ETHERNET);
1292        SMC_SELECT_BANK(dev, 1);
1293        for (i = 0; i < 6; ++i)
1294                dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1295        swap_to(FLASH);
1296
1297        dev->init = smc_init;
1298        dev->halt = smc_halt;
1299        dev->send = smc_send;
1300        dev->recv = smc_rcv;
1301        dev->write_hwaddr = smc_write_hwaddr;
1302        sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1303
1304        eth_register(dev);
1305        return 0;
1306}
1307