uboot/drivers/pci/pci_mvebu.c
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   1/*
   2 * PCIe driver for Marvell MVEBU SoCs
   3 *
   4 * Based on Barebox drivers/pci/pci-mvebu.c
   5 *
   6 * Ported to U-Boot by:
   7 * Anton Schubert <anton.schubert@gmx.de>
   8 * Stefan Roese <sr@denx.de>
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0
  11 */
  12
  13#include <common.h>
  14#include <pci.h>
  15#include <linux/errno.h>
  16#include <asm/io.h>
  17#include <asm/arch/cpu.h>
  18#include <asm/arch/soc.h>
  19#include <linux/mbus.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23/* PCIe unit register offsets */
  24#define SELECT(x, n)                    ((x >> n) & 1UL)
  25
  26#define PCIE_DEV_ID_OFF                 0x0000
  27#define PCIE_CMD_OFF                    0x0004
  28#define PCIE_DEV_REV_OFF                0x0008
  29#define  PCIE_BAR_LO_OFF(n)             (0x0010 + ((n) << 3))
  30#define  PCIE_BAR_HI_OFF(n)             (0x0014 + ((n) << 3))
  31#define PCIE_CAPAB_OFF                  0x0060
  32#define PCIE_CTRL_STAT_OFF              0x0068
  33#define PCIE_HEADER_LOG_4_OFF           0x0128
  34#define  PCIE_BAR_CTRL_OFF(n)           (0x1804 + (((n) - 1) * 4))
  35#define  PCIE_WIN04_CTRL_OFF(n)         (0x1820 + ((n) << 4))
  36#define  PCIE_WIN04_BASE_OFF(n)         (0x1824 + ((n) << 4))
  37#define  PCIE_WIN04_REMAP_OFF(n)        (0x182c + ((n) << 4))
  38#define PCIE_WIN5_CTRL_OFF              0x1880
  39#define PCIE_WIN5_BASE_OFF              0x1884
  40#define PCIE_WIN5_REMAP_OFF             0x188c
  41#define PCIE_CONF_ADDR_OFF              0x18f8
  42#define  PCIE_CONF_ADDR_EN              BIT(31)
  43#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  44#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
  45#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
  46#define  PCIE_CONF_FUNC(f)              (((f) & 0x7) << 8)
  47#define  PCIE_CONF_ADDR(dev, reg) \
  48        (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev))    | \
  49         PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
  50         PCIE_CONF_ADDR_EN)
  51#define PCIE_CONF_DATA_OFF              0x18fc
  52#define PCIE_MASK_OFF                   0x1910
  53#define  PCIE_MASK_ENABLE_INTS          (0xf << 24)
  54#define PCIE_CTRL_OFF                   0x1a00
  55#define  PCIE_CTRL_X1_MODE              BIT(0)
  56#define PCIE_STAT_OFF                   0x1a04
  57#define  PCIE_STAT_BUS                  (0xff << 8)
  58#define  PCIE_STAT_DEV                  (0x1f << 16)
  59#define  PCIE_STAT_LINK_DOWN            BIT(0)
  60#define PCIE_DEBUG_CTRL                 0x1a60
  61#define  PCIE_DEBUG_SOFT_RESET          BIT(20)
  62
  63struct resource {
  64        u32 start;
  65        u32 end;
  66};
  67
  68struct mvebu_pcie {
  69        struct pci_controller hose;
  70        char *name;
  71        void __iomem *base;
  72        void __iomem *membase;
  73        struct resource mem;
  74        void __iomem *iobase;
  75        u32 port;
  76        u32 lane;
  77        u32 lane_mask;
  78        pci_dev_t dev;
  79};
  80
  81#define to_pcie(_hc)    container_of(_hc, struct mvebu_pcie, pci)
  82
  83/*
  84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
  85 * into SoCs address space. Each controller will map 128M of MEM
  86 * and 64K of I/O space when registered.
  87 */
  88static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
  89#define PCIE_MEM_SIZE   (128 << 20)
  90
  91#if defined(CONFIG_ARMADA_38X)
  92#define PCIE_BASE(if)                                   \
  93        ((if) == 0 ?                                    \
  94         MVEBU_REG_PCIE0_BASE :                         \
  95         (MVEBU_REG_PCIE_BASE + 0x4000 * (if - 1)))
  96
  97/*
  98 * On A38x MV6820 these PEX ports are supported:
  99 *  0 - Port 0.0
 100 *  1 - Port 1.0
 101 *  2 - Port 2.0
 102 *  3 - Port 3.0
 103 */
 104#define MAX_PEX 4
 105static struct mvebu_pcie pcie_bus[MAX_PEX];
 106
 107static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
 108                                int *mem_target, int *mem_attr)
 109{
 110        u8 port[] = { 0, 1, 2, 3 };
 111        u8 lane[] = { 0, 0, 0, 0 };
 112        u8 target[] = { 8, 4, 4, 4 };
 113        u8 attr[] = { 0xe8, 0xe8, 0xd8, 0xb8 };
 114
 115        pcie->port = port[pex_idx];
 116        pcie->lane = lane[pex_idx];
 117        *mem_target = target[pex_idx];
 118        *mem_attr = attr[pex_idx];
 119}
 120#else
 121#define PCIE_BASE(if)                                                   \
 122        ((if) < 8 ?                                                     \
 123         (MVEBU_REG_PCIE_BASE + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) : \
 124         (MVEBU_REG_PCIE_BASE + 0x2000 + ((if) % 8) * 0x40000))
 125
 126/*
 127 * On AXP MV78460 these PEX ports are supported:
 128 *  0 - Port 0.0
 129 *  1 - Port 0.1
 130 *  2 - Port 0.2
 131 *  3 - Port 0.3
 132 *  4 - Port 1.0
 133 *  5 - Port 1.1
 134 *  6 - Port 1.2
 135 *  7 - Port 1.3
 136 *  8 - Port 2.0
 137 *  9 - Port 3.0
 138 */
 139#define MAX_PEX 10
 140static struct mvebu_pcie pcie_bus[MAX_PEX];
 141
 142static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
 143                                int *mem_target, int *mem_attr)
 144{
 145        u8 port[] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 3 };
 146        u8 lane[] = { 0, 1, 2, 3, 0, 1, 2, 3, 0, 0 };
 147        u8 target[] = { 4, 4, 4, 4, 8, 8, 8, 8, 4, 8 };
 148        u8 attr[] = { 0xe8, 0xd8, 0xb8, 0x78,
 149                      0xe8, 0xd8, 0xb8, 0x78,
 150                      0xf8, 0xf8 };
 151
 152        pcie->port = port[pex_idx];
 153        pcie->lane = lane[pex_idx];
 154        *mem_target = target[pex_idx];
 155        *mem_attr = attr[pex_idx];
 156}
 157#endif
 158
 159static int mvebu_pex_unit_is_x4(int pex_idx)
 160{
 161        int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
 162        u32 mask = (0x0f << (pex_unit * 8));
 163
 164        return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
 165}
 166
 167static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
 168{
 169        u32 val;
 170        val = readl(pcie->base + PCIE_STAT_OFF);
 171        return !(val & PCIE_STAT_LINK_DOWN);
 172}
 173
 174static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
 175{
 176        u32 stat;
 177
 178        stat = readl(pcie->base + PCIE_STAT_OFF);
 179        stat &= ~PCIE_STAT_BUS;
 180        stat |= busno << 8;
 181        writel(stat, pcie->base + PCIE_STAT_OFF);
 182}
 183
 184static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
 185{
 186        u32 stat;
 187
 188        stat = readl(pcie->base + PCIE_STAT_OFF);
 189        stat &= ~PCIE_STAT_DEV;
 190        stat |= devno << 16;
 191        writel(stat, pcie->base + PCIE_STAT_OFF);
 192}
 193
 194static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
 195{
 196        u32 stat;
 197
 198        stat = readl(pcie->base + PCIE_STAT_OFF);
 199        return (stat & PCIE_STAT_BUS) >> 8;
 200}
 201
 202static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
 203{
 204        u32 stat;
 205
 206        stat = readl(pcie->base + PCIE_STAT_OFF);
 207        return (stat & PCIE_STAT_DEV) >> 16;
 208}
 209
 210static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
 211{
 212        return container_of(hose, struct mvebu_pcie, hose);
 213}
 214
 215static int mvebu_pcie_read_config_dword(struct pci_controller *hose,
 216                pci_dev_t dev, int offset, u32 *val)
 217{
 218        struct mvebu_pcie *pcie = hose_to_pcie(hose);
 219        int local_bus = PCI_BUS(pcie->dev);
 220        int local_dev = PCI_DEV(pcie->dev);
 221        u32 reg;
 222
 223        /* Only allow one other device besides the local one on the local bus */
 224        if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
 225                if (local_dev == 0 && PCI_DEV(dev) != 1) {
 226                        /*
 227                         * If local dev is 0, the first other dev can
 228                         * only be 1
 229                         */
 230                        *val = 0xffffffff;
 231                        return 1;
 232                } else if (local_dev != 0 && PCI_DEV(dev) != 0) {
 233                        /*
 234                         * If local dev is not 0, the first other dev can
 235                         * only be 0
 236                         */
 237                        *val = 0xffffffff;
 238                        return 1;
 239                }
 240        }
 241
 242        /* write address */
 243        reg = PCIE_CONF_ADDR(dev, offset);
 244        writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
 245        *val = readl(pcie->base + PCIE_CONF_DATA_OFF);
 246
 247        return 0;
 248}
 249
 250static int mvebu_pcie_write_config_dword(struct pci_controller *hose,
 251                pci_dev_t dev, int offset, u32 val)
 252{
 253        struct mvebu_pcie *pcie = hose_to_pcie(hose);
 254        int local_bus = PCI_BUS(pcie->dev);
 255        int local_dev = PCI_DEV(pcie->dev);
 256
 257        /* Only allow one other device besides the local one on the local bus */
 258        if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
 259                if (local_dev == 0 && PCI_DEV(dev) != 1) {
 260                        /*
 261                         * If local dev is 0, the first other dev can
 262                         * only be 1
 263                         */
 264                        return 1;
 265                } else if (local_dev != 0 && PCI_DEV(dev) != 0) {
 266                        /*
 267                         * If local dev is not 0, the first other dev can
 268                         * only be 0
 269                         */
 270                        return 1;
 271                }
 272        }
 273
 274        writel(PCIE_CONF_ADDR(dev, offset), pcie->base + PCIE_CONF_ADDR_OFF);
 275        writel(val, pcie->base + PCIE_CONF_DATA_OFF);
 276
 277        return 0;
 278}
 279
 280/*
 281 * Setup PCIE BARs and Address Decode Wins:
 282 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 283 * WIN[0-3] -> DRAM bank[0-3]
 284 */
 285static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
 286{
 287        const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
 288        u32 size;
 289        int i;
 290
 291        /* First, disable and clear BARs and windows. */
 292        for (i = 1; i < 3; i++) {
 293                writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
 294                writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
 295                writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
 296        }
 297
 298        for (i = 0; i < 5; i++) {
 299                writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
 300                writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
 301                writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
 302        }
 303
 304        writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
 305        writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
 306        writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
 307
 308        /* Setup windows for DDR banks. Count total DDR size on the fly. */
 309        size = 0;
 310        for (i = 0; i < dram->num_cs; i++) {
 311                const struct mbus_dram_window *cs = dram->cs + i;
 312
 313                writel(cs->base & 0xffff0000,
 314                       pcie->base + PCIE_WIN04_BASE_OFF(i));
 315                writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
 316                writel(((cs->size - 1) & 0xffff0000) |
 317                       (cs->mbus_attr << 8) |
 318                       (dram->mbus_dram_target_id << 4) | 1,
 319                       pcie->base + PCIE_WIN04_CTRL_OFF(i));
 320
 321                size += cs->size;
 322        }
 323
 324        /* Round up 'size' to the nearest power of two. */
 325        if ((size & (size - 1)) != 0)
 326                size = 1 << fls(size);
 327
 328        /* Setup BAR[1] to all DRAM banks. */
 329        writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
 330        writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
 331        writel(((size - 1) & 0xffff0000) | 0x1,
 332               pcie->base + PCIE_BAR_CTRL_OFF(1));
 333}
 334
 335void pci_init_board(void)
 336{
 337        int mem_target, mem_attr, i;
 338        int bus = 0;
 339        u32 reg;
 340        u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4);
 341
 342        /* Check SoC Control Power State */
 343        debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n",
 344              __func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1),
 345              SELECT(soc_ctrl, 2));
 346
 347        for (i = 0; i < MAX_PEX; i++) {
 348                struct mvebu_pcie *pcie = &pcie_bus[i];
 349                struct pci_controller *hose = &pcie->hose;
 350
 351                /* Get port number, lane number and memory target / attr */
 352                mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
 353
 354                /* Don't read at all from pci registers if port power is down */
 355                if (SELECT(soc_ctrl, pcie->port) == 0) {
 356                        if (pcie->lane == 0)
 357                                debug("%s: skipping port %d\n", __func__, pcie->port);
 358                        continue;
 359                }
 360
 361                pcie->base = (void __iomem *)PCIE_BASE(i);
 362
 363                /* Check link and skip ports that have no link */
 364                if (!mvebu_pcie_link_up(pcie)) {
 365                        debug("%s: PCIe %d.%d - down\n", __func__,
 366                              pcie->port, pcie->lane);
 367                        continue;
 368                }
 369                debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
 370                      pcie->port, pcie->lane, (u32)pcie->base);
 371
 372                /* Read Id info and local bus/dev */
 373                debug("direct conf read %08x, local bus %d, local dev %d\n",
 374                      readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
 375                      mvebu_pcie_get_local_dev_nr(pcie));
 376
 377                mvebu_pcie_set_local_bus_nr(pcie, bus);
 378                mvebu_pcie_set_local_dev_nr(pcie, 0);
 379                pcie->dev = PCI_BDF(bus, 0, 0);
 380
 381                pcie->mem.start = (u32)mvebu_pcie_membase;
 382                pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
 383                mvebu_pcie_membase += PCIE_MEM_SIZE;
 384
 385                if (mvebu_mbus_add_window_by_id(mem_target, mem_attr,
 386                                                (phys_addr_t)pcie->mem.start,
 387                                                PCIE_MEM_SIZE)) {
 388                        printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
 389                               (u32)pcie->mem.start, PCIE_MEM_SIZE);
 390                }
 391
 392                /* Setup windows and configure host bridge */
 393                mvebu_pcie_setup_wins(pcie);
 394
 395                /* Master + slave enable. */
 396                reg = readl(pcie->base + PCIE_CMD_OFF);
 397                reg |= PCI_COMMAND_MEMORY;
 398                reg |= PCI_COMMAND_MASTER;
 399                reg |= BIT(10);         /* disable interrupts */
 400                writel(reg, pcie->base + PCIE_CMD_OFF);
 401
 402                /* Setup U-Boot PCI Controller */
 403                hose->first_busno = 0;
 404                hose->current_busno = bus;
 405
 406                /* PCI memory space */
 407                pci_set_region(hose->regions + 0, pcie->mem.start,
 408                               pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
 409                pci_set_region(hose->regions + 1,
 410                               0, 0,
 411                               gd->ram_size,
 412                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 413                hose->region_count = 2;
 414
 415                pci_set_ops(hose,
 416                            pci_hose_read_config_byte_via_dword,
 417                            pci_hose_read_config_word_via_dword,
 418                            mvebu_pcie_read_config_dword,
 419                            pci_hose_write_config_byte_via_dword,
 420                            pci_hose_write_config_word_via_dword,
 421                            mvebu_pcie_write_config_dword);
 422                pci_register_hose(hose);
 423
 424                hose->last_busno = pci_hose_scan(hose);
 425
 426                /* Set BAR0 to internal registers */
 427                writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
 428                writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
 429
 430                bus = hose->last_busno + 1;
 431
 432                /* need to skip more for X4 links, otherwise scan will hang */
 433                if (mvebu_soc_family() == MVEBU_SOC_AXP) {
 434                        if (mvebu_pex_unit_is_x4(i))
 435                                i += 3;
 436                }
 437        }
 438}
 439