1/* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12#ifndef _CONFIG_EDMINIV2_H 13#define _CONFIG_EDMINIV2_H 14 15/* 16 * SPL 17 */ 18 19#define CONFIG_SPL_TEXT_BASE 0xffff0000 20#define CONFIG_SPL_MAX_SIZE 0x0000fff0 21#define CONFIG_SPL_STACK 0x00020000 22#define CONFIG_SPL_BSS_START_ADDR 0x00020000 23#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 24#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 25#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 26#define CONFIG_SYS_UBOOT_BASE 0xfff90000 27#define CONFIG_SYS_UBOOT_START 0x00800000 28 29/* 30 * High Level Configuration Options (easy to change) 31 */ 32 33#define CONFIG_MARVELL 1 34#define CONFIG_FEROCEON 1 /* CPU Core subversion */ 35#define CONFIG_88F5182 1 /* SOC Name */ 36 37#include <asm/arch/orion5x.h> 38/* 39 * CLKs configurations 40 */ 41 42/* 43 * Board-specific values for Orion5x MPP low level init: 44 * - MPPs 12 to 15 are SATA LEDs (mode 5) 45 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 46 * MPP16 to MPP19, mode 0 for others 47 */ 48 49#define ORION5X_MPP0_7 0x00000003 50#define ORION5X_MPP8_15 0x55550000 51#define ORION5X_MPP16_23 0x00005555 52 53/* 54 * Board-specific values for Orion5x GPIO low level init: 55 * - GPIO3 is input (RTC interrupt) 56 * - GPIO16 is Power LED control (0 = on, 1 = off) 57 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 58 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 59 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 60 * - GPIO22 is SATA disk power status () 61 * - GPIO23 is supply status for SATA disk () 62 * - GPIO24 is supply control for board (write 1 to power off) 63 * Last GPIO is 25, further bits are supposed to be 0. 64 * Enable mask has ones for INPUT, 0 for OUTPUT. 65 * Default is LED ON, board ON :) 66 */ 67 68#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 69#define ORION5X_GPIO_OUT_VALUE 0x00000000 70#define ORION5X_GPIO_IN_POLARITY 0x000000d0 71 72/* 73 * NS16550 Configuration 74 */ 75 76#define CONFIG_SYS_NS16550_SERIAL 77#define CONFIG_SYS_NS16550_REG_SIZE (-4) 78#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 79#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 80 81/* 82 * Serial Port configuration 83 * The following definitions let you select what serial you want to use 84 * for your console driver. 85 */ 86 87#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 88#define CONFIG_SYS_BAUDRATE_TABLE \ 89 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 90 91/* 92 * FLASH configuration 93 */ 94 95#define CONFIG_SYS_FLASH_CFI 96#define CONFIG_FLASH_CFI_DRIVER 97#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 98#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 99#define CONFIG_SYS_FLASH_BASE 0xfff80000 100 101/* auto boot */ 102 103/* 104 * For booting Linux, the board info and command line data 105 * have to be in the first 8 MB of memory, since this is 106 * the maximum mapped by the Linux kernel during initialization. 107 */ 108#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 109#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 110#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 111 112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 113/* 114 * Commands configuration 115 */ 116 117/* 118 * Network 119 */ 120 121#ifdef CONFIG_CMD_NET 122#define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 123#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 124#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 125#define CONFIG_PHY_BASE_ADR 0x8 126#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 127#define CONFIG_NETCONSOLE /* include NetConsole support */ 128#define CONFIG_MII /* expose smi ove miiphy interface */ 129#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 130#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 131#endif 132 133/* 134 * IDE 135 */ 136#ifdef CONFIG_IDE 137#define __io 138#define CONFIG_IDE_PREINIT 139/* ED Mini V has an IDE-compatible SATA connector for port 1 */ 140#define CONFIG_MVSATA_IDE_USE_PORT1 141/* Needs byte-swapping for ATA data register */ 142#define CONFIG_IDE_SWAP_IO 143/* Data, registers and alternate blocks are at the same offset */ 144#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 145#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 146#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 147/* Each 8-bit ATA register is aligned to a 4-bytes address */ 148#define CONFIG_SYS_ATA_STRIDE 4 149/* Controller supports 48-bits LBA addressing */ 150#define CONFIG_LBA48 151/* A single bus, a single device */ 152#define CONFIG_SYS_IDE_MAXBUS 1 153#define CONFIG_SYS_IDE_MAXDEVICE 1 154/* ATA registers base is at SATA controller base */ 155#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 156/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 157#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 158/* end of IDE defines */ 159#endif /* CMD_IDE */ 160 161/* 162 * Common USB/EHCI configuration 163 */ 164#ifdef CONFIG_CMD_USB 165#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 166#endif /* CONFIG_CMD_USB */ 167 168/* 169 * I2C related stuff 170 */ 171#ifdef CONFIG_CMD_I2C 172#define CONFIG_SYS_I2C 173#define CONFIG_SYS_I2C_MVTWSI 174#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 175#define CONFIG_SYS_I2C_SLAVE 0x0 176#define CONFIG_SYS_I2C_SPEED 100000 177#endif 178 179/* 180 * Environment variables configurations 181 */ 182#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 183#define CONFIG_ENV_SIZE 0x2000 184#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 185 186/* 187 * Size of malloc() pool 188 */ 189#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 190 191/* 192 * Other required minimal configurations 193 */ 194#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 195#define CONFIG_NR_DRAM_BANKS 1 196 197#define CONFIG_SYS_LOAD_ADDR 0x00800000 198#define CONFIG_SYS_MEMTEST_START 0x00400000 199#define CONFIG_SYS_MEMTEST_END 0x007fffff 200#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 201 202/* Enable command line editing */ 203 204/* provide extensive help */ 205 206/* additions for new relocation code, must be added to all boards */ 207#define CONFIG_SYS_SDRAM_BASE 0 208#define CONFIG_SYS_INIT_SP_ADDR \ 209 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 210 211#endif /* _CONFIG_EDMINIV2_H */ 212