LXR uboot/include/configs/lager.h

   1/*
   2 * include/configs/lager.h
   3 *     This file is lager board configuration.
   4 *
   5 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   6 *
   7 * SPDX-License-Identifier: GPL-2.0
   8 */
   9
  10#ifndef __LAGER_H
  11#define __LAGER_H
  12
  13#undef DEBUG
  14#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
  15
  16#include "rcar-gen2-common.h"
  17
  18/* STACK */
  19#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
  20#define CONFIG_SYS_INIT_SP_ADDR         0xB003FFFC
  21#else
  22#define CONFIG_SYS_INIT_SP_ADDR         0xE827FFFC
  23#endif
  24#define STACK_AREA_SIZE                 0xC000
  25#define LOW_LEVEL_MERAM_STACK   \
  26                (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  27
  28/* MEMORY */
  29#define RCAR_GEN2_SDRAM_BASE            0x40000000
  30#define RCAR_GEN2_SDRAM_SIZE            (2048u * 1024 * 1024)
  31#define RCAR_GEN2_UBOOT_SDRAM_SIZE      (512 * 1024 * 1024)
  32
  33/* SCIF */
  34
  35/* SPI */
  36#define CONFIG_SPI
  37
  38/* SH Ether */
  39#define CONFIG_SH_ETHER_USE_PORT        0
  40#define CONFIG_SH_ETHER_PHY_ADDR        0x1
  41#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  42#define CONFIG_SH_ETHER_ALIGNE_SIZE     64
  43#define CONFIG_SH_ETHER_CACHE_WRITEBACK
  44#define CONFIG_SH_ETHER_CACHE_INVALIDATE
  45#define CONFIG_BITBANGMII
  46#define CONFIG_BITBANGMII_MULTI
  47
  48/* I2C */
  49#define CONFIG_SYS_I2C
  50#define CONFIG_SYS_I2C_RCAR
  51#define CONFIG_SYS_RCAR_I2C0_SPEED      400000
  52#define CONFIG_SYS_RCAR_I2C1_SPEED      400000
  53#define CONFIG_SYS_RCAR_I2C2_SPEED      400000
  54#define CONFIG_SYS_RCAR_I2C3_SPEED      400000
  55#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS     4
  56
  57#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
  58
  59/* Board Clock */
  60#define RMOBILE_XTAL_CLK        20000000u
  61#define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
  62#define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
  63#define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
  64#define CONFIG_PLL1_DIV2_CLK_FREQ       (CONFIG_PLL1_CLK_FREQ / 2)
  65#define CONFIG_MP_CLK_FREQ      (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
  66#define CONFIG_HP_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 12)
  67
  68#define CONFIG_SYS_TMU_CLK_DIV  4
  69
  70/* USB */
  71#define CONFIG_USB_EHCI_RMOBILE
  72#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  73
  74/* MMC */
  75#define CONFIG_SH_MMCIF
  76#define CONFIG_SH_MMCIF_ADDR            0xEE220000
  77#define CONFIG_SH_MMCIF_CLK             97500000
  78
  79/* Module stop status bits */
  80/* INTC-RT */
  81#define CONFIG_SMSTP0_ENA       0x00400000
  82/* MSIF */
  83#define CONFIG_SMSTP2_ENA       0x00002000
  84/* INTC-SYS, IRQC */
  85#define CONFIG_SMSTP4_ENA       0x00000180
  86/* SCIF0 */
  87#define CONFIG_SMSTP7_ENA       0x00200000
  88
  89/* SDHI */
  90#define CONFIG_SH_SDHI_FREQ     97500000
  91
  92#endif  /* __LAGER_H */
  93