1/* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6#ifndef __CONFIG_SOCFPGA_COMMON_H__ 7#define __CONFIG_SOCFPGA_COMMON_H__ 8 9/* Virtual target or real hardware */ 10#undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12/* 13 * High level configuration 14 */ 15#define CONFIG_DISPLAY_BOARDINFO_LATE 16#define CONFIG_CLOCKS 17 18#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22/* add target to build it automatically upon "make" */ 23#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25/* 26 * Memory configurations 27 */ 28#define CONFIG_NR_DRAM_BANKS 1 29#define PHYS_SDRAM_1 0x0 30#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33#if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39#endif 40#define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42#define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 47/* 48 * U-Boot general configurations 49 */ 50#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 51 /* Print buffer size */ 52#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 53#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 54 /* Boot argument buffer size */ 55 56#ifndef CONFIG_SYS_HOSTNAME 57#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 58#endif 59 60/* 61 * Cache 62 */ 63#define CONFIG_SYS_L2_PL310 64#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 65 66/* 67 * EPCS/EPCQx1 Serial Flash Controller 68 */ 69#ifdef CONFIG_ALTERA_SPI 70#define CONFIG_SF_DEFAULT_SPEED 30000000 71/* 72 * The base address is configurable in QSys, each board must specify the 73 * base address based on it's particular FPGA configuration. Please note 74 * that the address here is incremented by 0x400 from the Base address 75 * selected in QSys, since the SPI registers are at offset +0x400. 76 * #define CONFIG_SYS_SPI_BASE 0xff240400 77 */ 78#endif 79 80/* 81 * Ethernet on SoC (EMAC) 82 */ 83#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 84#define CONFIG_DW_ALTDESCRIPTOR 85#define CONFIG_MII 86#endif 87 88/* 89 * FPGA Driver 90 */ 91#ifdef CONFIG_CMD_FPGA 92#define CONFIG_FPGA_COUNT 1 93#endif 94 95/* 96 * L4 OSC1 Timer 0 97 */ 98/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 99#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 100#define CONFIG_SYS_TIMER_COUNTS_DOWN 101#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 102#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 103#define CONFIG_SYS_TIMER_RATE 2400000 104#else 105#define CONFIG_SYS_TIMER_RATE 25000000 106#endif 107 108/* 109 * L4 Watchdog 110 */ 111#ifdef CONFIG_HW_WATCHDOG 112#define CONFIG_DESIGNWARE_WATCHDOG 113#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 114#define CONFIG_DW_WDT_CLOCK_KHZ 25000 115#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 116#endif 117 118/* 119 * MMC Driver 120 */ 121#ifdef CONFIG_CMD_MMC 122#define CONFIG_BOUNCE_BUFFER 123/* FIXME */ 124/* using smaller max blk cnt to avoid flooding the limited stack we have */ 125#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 126#endif 127 128/* 129 * NAND Support 130 */ 131#ifdef CONFIG_NAND_DENALI 132#define CONFIG_SYS_MAX_NAND_DEVICE 1 133#define CONFIG_SYS_NAND_ONFI_DETECTION 134#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 135#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 136#endif 137 138/* 139 * I2C support 140 */ 141#define CONFIG_SYS_I2C 142#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 143#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 144#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 145#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 146/* Using standard mode which the speed up to 100Kb/s */ 147#define CONFIG_SYS_I2C_SPEED 100000 148#define CONFIG_SYS_I2C_SPEED1 100000 149#define CONFIG_SYS_I2C_SPEED2 100000 150#define CONFIG_SYS_I2C_SPEED3 100000 151/* Address of device when used as slave */ 152#define CONFIG_SYS_I2C_SLAVE 0x02 153#define CONFIG_SYS_I2C_SLAVE1 0x02 154#define CONFIG_SYS_I2C_SLAVE2 0x02 155#define CONFIG_SYS_I2C_SLAVE3 0x02 156#ifndef __ASSEMBLY__ 157/* Clock supplied to I2C controller in unit of MHz */ 158unsigned int cm_get_l4_sp_clk_hz(void); 159#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 160#endif 161 162/* 163 * QSPI support 164 */ 165/* Enable multiple SPI NOR flash manufacturers */ 166#ifndef CONFIG_SPL_BUILD 167#define CONFIG_SPI_FLASH_MTD 168#define CONFIG_MTD_DEVICE 169#define CONFIG_MTD_PARTITIONS 170#endif 171/* QSPI reference clock */ 172#ifndef __ASSEMBLY__ 173unsigned int cm_get_qspi_controller_clk_hz(void); 174#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 175#endif 176 177/* 178 * Designware SPI support 179 */ 180 181/* 182 * Serial Driver 183 */ 184#define CONFIG_SYS_NS16550_SERIAL 185#define CONFIG_SYS_NS16550_REG_SIZE -4 186#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 187#define CONFIG_SYS_NS16550_CLK 1000000 188#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 189#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 190#define CONFIG_SYS_NS16550_CLK 100000000 191#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 192#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 193#define CONFIG_SYS_NS16550_CLK 50000000 194#endif 195#define CONFIG_CONS_INDEX 1 196 197/* 198 * USB 199 */ 200 201/* 202 * USB Gadget (DFU, UMS) 203 */ 204#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 205#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 206#define DFU_DEFAULT_POLL_TIMEOUT 300 207 208/* USB IDs */ 209#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 210#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 211#endif 212 213/* 214 * U-Boot environment 215 */ 216#if !defined(CONFIG_ENV_SIZE) 217#define CONFIG_ENV_SIZE (8 * 1024) 218#endif 219 220/* Environment for SDMMC boot */ 221#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 222#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 223#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 224#endif 225 226/* Environment for QSPI boot */ 227#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 228#define CONFIG_ENV_OFFSET 0x00100000 229#define CONFIG_ENV_SECT_SIZE (64 * 1024) 230#endif 231 232/* 233 * mtd partitioning for serial NOR flash 234 * 235 * device nor0 <ff705000.spi.0>, # parts = 6 236 * #: name size offset mask_flags 237 * 0: u-boot 0x00100000 0x00000000 0 238 * 1: env1 0x00040000 0x00100000 0 239 * 2: env2 0x00040000 0x00140000 0 240 * 3: UBI 0x03e80000 0x00180000 0 241 * 4: boot 0x00e80000 0x00180000 0 242 * 5: rootfs 0x01000000 0x01000000 0 243 * 244 */ 245 246/* 247 * SPL 248 * 249 * SRAM Memory layout: 250 * 251 * 0xFFFF_0000 ...... Start of SRAM 252 * 0xFFFF_xxxx ...... Top of stack (grows down) 253 * 0xFFFF_yyyy ...... Malloc area 254 * 0xFFFF_zzzz ...... Global Data 255 * 0xFFFF_FF00 ...... End of SRAM 256 */ 257#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 258#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 259 260/* SPL SDMMC boot support */ 261#ifdef CONFIG_SPL_MMC_SUPPORT 262#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 263#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 264#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 265#endif 266#else 267#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 268#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 269#endif 270#endif 271 272/* SPL QSPI boot support */ 273#ifdef CONFIG_SPL_SPI_SUPPORT 274#define CONFIG_SPL_SPI_LOAD 275#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 276#endif 277 278/* SPL NAND boot support */ 279#ifdef CONFIG_SPL_NAND_SUPPORT 280#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 281#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 282#endif 283 284/* 285 * Stack setup 286 */ 287#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 288 289/* Extra Environment */ 290#ifndef CONFIG_SPL_BUILD 291 292#ifdef CONFIG_CMD_DHCP 293#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 294#else 295#define BOOT_TARGET_DEVICES_DHCP(func) 296#endif 297 298#ifdef CONFIG_CMD_PXE 299#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 300#else 301#define BOOT_TARGET_DEVICES_PXE(func) 302#endif 303 304#ifdef CONFIG_CMD_MMC 305#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 306#else 307#define BOOT_TARGET_DEVICES_MMC(func) 308#endif 309 310#define BOOT_TARGET_DEVICES(func) \ 311 BOOT_TARGET_DEVICES_MMC(func) \ 312 BOOT_TARGET_DEVICES_PXE(func) \ 313 BOOT_TARGET_DEVICES_DHCP(func) 314 315#include <config_distro_bootcmd.h> 316 317#ifndef CONFIG_EXTRA_ENV_SETTINGS 318#define CONFIG_EXTRA_ENV_SETTINGS \ 319 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 320 "bootm_size=0xa000000\0" \ 321 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 322 "fdt_addr_r=0x02000000\0" \ 323 "scriptaddr=0x02100000\0" \ 324 "pxefile_addr_r=0x02200000\0" \ 325 "ramdisk_addr_r=0x02300000\0" \ 326 BOOTENV 327 328#endif 329#endif 330 331#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 332