LXR uboot/arch/arm/include/asm/arch-fsl-layerscape/soc.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2017 NXP
   4 * Copyright 2015 Freescale Semiconductor
   5 */
   6
   7#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
   8#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
   9
  10#ifndef __ASSEMBLY__
  11#include <linux/types.h>
  12#ifdef CONFIG_FSL_LSCH2
  13#include <asm/arch/immap_lsch2.h>
  14#endif
  15#ifdef CONFIG_FSL_LSCH3
  16#include <asm/arch/immap_lsch3.h>
  17#endif
  18#endif
  19
  20#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
  21#define gur_in32(a)       in_le32(a)
  22#define gur_out32(a, v)   out_le32(a, v)
  23#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
  24#define gur_in32(a)       in_be32(a)
  25#define gur_out32(a, v)   out_be32(a, v)
  26#endif
  27
  28#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
  29#define scfg_in32(a)       in_le32(a)
  30#define scfg_out32(a, v)   out_le32(a, v)
  31#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
  32#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
  33#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
  34#define scfg_in32(a)       in_be32(a)
  35#define scfg_out32(a, v)   out_be32(a, v)
  36#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
  37#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
  38#endif
  39
  40#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
  41#define pex_lut_in32(a)       in_le32(a)
  42#define pex_lut_out32(a, v)   out_le32(a, v)
  43#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
  44#define pex_lut_in32(a)       in_be32(a)
  45#define pex_lut_out32(a, v)   out_be32(a, v)
  46#endif
  47#ifndef __ASSEMBLY__
  48struct cpu_type {
  49        char name[15];
  50        u32 soc_ver;
  51        u32 num_cores;
  52};
  53
  54#define CPU_TYPE_ENTRY(n, v, nc) \
  55        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
  56#endif
  57#define SVR_WO_E                0xFFFFFE
  58#define SVR_LS1012A             0x870400
  59#define SVR_LS1043A             0x879200
  60#define SVR_LS1023A             0x879208
  61#define SVR_LS1046A             0x870700
  62#define SVR_LS1026A             0x870708
  63#define SVR_LS1048A             0x870320
  64#define SVR_LS1084A             0x870302
  65#define SVR_LS1088A             0x870300
  66#define SVR_LS1044A             0x870322
  67#define SVR_LS2045A             0x870120
  68#define SVR_LS2080A             0x870110
  69#define SVR_LS2085A             0x870100
  70#define SVR_LS2040A             0x870130
  71#define SVR_LS2088A             0x870900
  72#define SVR_LS2084A             0x870910
  73#define SVR_LS2048A             0x870920
  74#define SVR_LS2044A             0x870930
  75#define SVR_LS2081A             0x870918
  76#define SVR_LS2041A             0x870914
  77
  78#define SVR_MAJ(svr)            (((svr) >> 4) & 0xf)
  79#define SVR_MIN(svr)            (((svr) >> 0) & 0xf)
  80#define SVR_REV(svr)            (((svr) >> 0) & 0xff)
  81#define SVR_SOC_VER(svr)        (((svr) >> 8) & SVR_WO_E)
  82#define IS_E_PROCESSOR(svr)     (!((svr >> 8) & 0x1))
  83#define IS_SVR_REV(svr, maj, min) \
  84                ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
  85#define SVR_DEV(svr)            ((svr) >> 8)
  86#define IS_SVR_DEV(svr, dev)    (((svr) >> 16) == (dev))
  87
  88/* ahci port register default value */
  89#define AHCI_PORT_PHY_1_CFG    0xa003fffe
  90#define AHCI_PORT_PHY2_CFG      0x28184d1f
  91#define AHCI_PORT_PHY3_CFG      0x0e081509
  92#define AHCI_PORT_TRANS_CFG    0x08000029
  93#define AHCI_PORT_AXICC_CFG     0x3fffffff
  94
  95#ifndef __ASSEMBLY__
  96/* AHCI (sata) register map */
  97struct ccsr_ahci {
  98        u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
  99        u32 pcfg;       /* port config */
 100        u32 ppcfg;      /* port phy1 config */
 101        u32 pp2c;       /* port phy2 config */
 102        u32 pp3c;       /* port phy3 config */
 103        u32 pp4c;       /* port phy4 config */
 104        u32 pp5c;       /* port phy5 config */
 105        u32 axicc;      /* AXI cache control */
 106        u32 paxic;      /* port AXI config */
 107        u32 axipc;      /* AXI PROT control */
 108        u32 ptc;        /* port Trans Config */
 109        u32 pts;        /* port Trans Status */
 110        u32 plc;        /* port link config */
 111        u32 plc1;       /* port link config1 */
 112        u32 plc2;       /* port link config2 */
 113        u32 pls;        /* port link status */
 114        u32 pls1;       /* port link status1 */
 115        u32 pcmdc;      /* port CMD config */
 116        u32 ppcs;       /* port phy control status */
 117        u32 pberr;      /* port 0/1 BIST error */
 118        u32 cmds;       /* port 0/1 CMD status error */
 119};
 120
 121#ifdef CONFIG_FSL_LSCH3
 122void fsl_lsch3_early_init_f(void);
 123int get_core_volt_from_fuse(void);
 124#elif defined(CONFIG_FSL_LSCH2)
 125void fsl_lsch2_early_init_f(void);
 126int setup_chip_volt(void);
 127/* Setup core vdd in unit mV */
 128int board_setup_core_volt(u32 vdd);
 129#ifdef CONFIG_FSL_PFE
 130void init_pfe_scfg_dcfg_regs(void);
 131#endif
 132#endif
 133
 134void cpu_name(char *name);
 135#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 136void erratum_a009635(void);
 137#endif
 138
 139#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 140void erratum_a010315(void);
 141#endif
 142
 143bool soc_has_dp_ddr(void);
 144bool soc_has_aiop(void);
 145#endif
 146
 147#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
 148