LXR uboot/arch/arm/include/asm/arch-lpc32xx/config.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Common definitions for LPC32XX board configurations
   4 *
   5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   6 */
   7
   8#ifndef _LPC32XX_CONFIG_H
   9#define _LPC32XX_CONFIG_H
  10
  11
  12/* Basic CPU architecture */
  13#define CONFIG_ARCH_CPU_INIT
  14
  15#define CONFIG_NR_DRAM_BANKS_MAX        2
  16
  17/* UART configuration */
  18#if     (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
  19        (CONFIG_SYS_LPC32XX_UART == 7)
  20#if !defined(CONFIG_LPC32XX_HSUART)
  21#define CONFIG_LPC32XX_HSUART
  22#endif
  23#endif
  24
  25#if !defined(CONFIG_SYS_NS16550_CLK)
  26#define CONFIG_SYS_NS16550_CLK          13000000
  27#endif
  28
  29#define CONFIG_SYS_BAUDRATE_TABLE       \
  30                { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
  31
  32/* Ethernet */
  33#define LPC32XX_ETH_BASE ETHERNET_BASE
  34
  35/* NAND */
  36#if defined(CONFIG_NAND_LPC32XX_SLC)
  37#define NAND_LARGE_BLOCK_PAGE_SIZE      0x800
  38#define NAND_SMALL_BLOCK_PAGE_SIZE      0x200
  39
  40#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
  41#define CONFIG_SYS_NAND_PAGE_SIZE       NAND_LARGE_BLOCK_PAGE_SIZE
  42#endif
  43
  44#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
  45#define CONFIG_SYS_NAND_OOBSIZE         64
  46#define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
  47                                          48, 49, 50, 51, 52, 53, 54, 55, \
  48                                          56, 57, 58, 59, 60, 61, 62, 63, }
  49#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  50#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
  51#define CONFIG_SYS_NAND_OOBSIZE         16
  52#define CONFIG_SYS_NAND_ECCPOS          { 10, 11, 12, 13, 14, 15, }
  53#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
  54#else
  55#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
  56#endif
  57
  58#define CONFIG_SYS_NAND_ECCSIZE         0x100
  59#define CONFIG_SYS_NAND_ECCBYTES        3
  60#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  61                                                CONFIG_SYS_NAND_PAGE_SIZE)
  62#endif  /* CONFIG_NAND_LPC32XX_SLC */
  63
  64/* NOR Flash */
  65#if defined(CONFIG_SYS_FLASH_CFI)
  66#define CONFIG_FLASH_CFI_DRIVER
  67#define CONFIG_SYS_FLASH_PROTECTION
  68#endif
  69
  70/* USB OHCI */
  71#if defined(CONFIG_USB_OHCI_LPC32XX)
  72#define CONFIG_USB_OHCI_NEW
  73#define CONFIG_SYS_USB_OHCI_CPU_INIT
  74#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
  75#define CONFIG_SYS_USB_OHCI_REGS_BASE           USB_BASE
  76#define CONFIG_SYS_USB_OHCI_SLOT_NAME           "lpc32xx-ohci"
  77#endif
  78
  79#endif /* _LPC32XX_CONFIG_H */
  80