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5#ifndef __ASM_ARCH_MX6_DDR_H__
6#define __ASM_ARCH_MX6_DDR_H__
7
8#ifndef CONFIG_SPL_BUILD
9#ifdef CONFIG_MX6Q
10#include "mx6q-ddr.h"
11#else
12#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
13#include "mx6dl-ddr.h"
14#else
15#ifdef CONFIG_MX6SX
16#include "mx6sx-ddr.h"
17#else
18#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
19#include "mx6ul-ddr.h"
20#else
21#ifdef CONFIG_MX6SL
22#include "mx6sl-ddr.h"
23#else
24#error "Please select cpu"
25#endif
26#endif
27#endif
28#endif
29#endif
30#else
31
32enum {
33 DDR_TYPE_DDR3,
34 DDR_TYPE_LPDDR2,
35};
36
37
38struct mmdc_p_regs {
39 u32 mdctl;
40 u32 mdpdc;
41 u32 mdotc;
42 u32 mdcfg0;
43 u32 mdcfg1;
44 u32 mdcfg2;
45 u32 mdmisc;
46 u32 mdscr;
47 u32 mdref;
48 u32 res1[2];
49 u32 mdrwd;
50 u32 mdor;
51 u32 mdmrr;
52 u32 mdcfg3lp;
53 u32 mdmr4;
54 u32 mdasp;
55 u32 res2[239];
56 u32 maarcr;
57 u32 mapsr;
58 u32 maexidr0;
59 u32 maexidr1;
60 u32 madpcr0;
61 u32 madpcr1;
62 u32 madpsr0;
63 u32 madpsr1;
64 u32 madpsr2;
65 u32 madpsr3;
66 u32 madpsr4;
67 u32 madpsr5;
68 u32 masbs0;
69 u32 masbs1;
70 u32 res3[2];
71 u32 magenp;
72 u32 res4[239];
73 u32 mpzqhwctrl;
74 u32 mpzqswctrl;
75 u32 mpwlgcr;
76 u32 mpwldectrl0;
77 u32 mpwldectrl1;
78 u32 mpwldlst;
79 u32 mpodtctrl;
80 u32 mprddqby0dl;
81 u32 mprddqby1dl;
82 u32 mprddqby2dl;
83 u32 mprddqby3dl;
84 u32 mpwrdqby0dl;
85 u32 mpwrdqby1dl;
86 u32 mpwrdqby2dl;
87 u32 mpwrdqby3dl;
88 u32 mpdgctrl0;
89 u32 mpdgctrl1;
90 u32 mpdgdlst0;
91 u32 mprddlctl;
92 u32 mprddlst;
93 u32 mpwrdlctl;
94 u32 mpwrdlst;
95 u32 mpsdctrl;
96 u32 mpzqlp2ctl;
97 u32 mprddlhwctl;
98 u32 mpwrdlhwctl;
99 u32 mprddlhwst0;
100 u32 mprddlhwst1;
101 u32 mpwrdlhwst0;
102 u32 mpwrdlhwst1;
103 u32 mpwlhwerr;
104 u32 mpdghwst0;
105 u32 mpdghwst1;
106 u32 mpdghwst2;
107 u32 mpdghwst3;
108 u32 mppdcmpr1;
109 u32 mppdcmpr2;
110 u32 mpswdar0;
111 u32 mpswdrdr0;
112 u32 mpswdrdr1;
113 u32 mpswdrdr2;
114 u32 mpswdrdr3;
115 u32 mpswdrdr4;
116 u32 mpswdrdr5;
117 u32 mpswdrdr6;
118 u32 mpswdrdr7;
119 u32 mpmur0;
120 u32 mpwrcadl;
121 u32 mpdccr;
122};
123
124#define MX6SL_IOM_DDR_BASE 0x020e0300
125struct mx6sl_iomux_ddr_regs {
126 u32 dram_cas;
127 u32 dram_cs0_b;
128 u32 dram_cs1_b;
129 u32 dram_dqm0;
130 u32 dram_dqm1;
131 u32 dram_dqm2;
132 u32 dram_dqm3;
133 u32 dram_ras;
134 u32 dram_reset;
135 u32 dram_sdba0;
136 u32 dram_sdba1;
137 u32 dram_sdba2;
138 u32 dram_sdcke0;
139 u32 dram_sdcke1;
140 u32 dram_sdclk_0;
141 u32 dram_odt0;
142 u32 dram_odt1;
143 u32 dram_sdqs0;
144 u32 dram_sdqs1;
145 u32 dram_sdqs2;
146 u32 dram_sdqs3;
147 u32 dram_sdwe_b;
148};
149
150#define MX6SL_IOM_GRP_BASE 0x020e0500
151struct mx6sl_iomux_grp_regs {
152 u32 res1[43];
153 u32 grp_addds;
154 u32 grp_ddrmode_ctl;
155 u32 grp_ddrpke;
156 u32 grp_ddrpk;
157 u32 grp_ddrhys;
158 u32 grp_ddrmode;
159 u32 grp_b0ds;
160 u32 grp_ctlds;
161 u32 grp_b1ds;
162 u32 grp_ddr_type;
163 u32 grp_b2ds;
164 u32 grp_b3ds;
165};
166
167#define MX6UL_IOM_DDR_BASE 0x020e0200
168struct mx6ul_iomux_ddr_regs {
169 u32 res1[17];
170 u32 dram_dqm0;
171 u32 dram_dqm1;
172 u32 dram_ras;
173 u32 dram_cas;
174 u32 dram_cs0;
175 u32 dram_cs1;
176 u32 dram_sdwe_b;
177 u32 dram_odt0;
178 u32 dram_odt1;
179 u32 dram_sdba0;
180 u32 dram_sdba1;
181 u32 dram_sdba2;
182 u32 dram_sdcke0;
183 u32 dram_sdcke1;
184 u32 dram_sdclk_0;
185 u32 dram_sdqs0;
186 u32 dram_sdqs1;
187 u32 dram_reset;
188};
189
190#define MX6UL_IOM_GRP_BASE 0x020e0400
191struct mx6ul_iomux_grp_regs {
192 u32 res1[36];
193 u32 grp_addds;
194 u32 grp_ddrmode_ctl;
195 u32 grp_b0ds;
196 u32 grp_ddrpk;
197 u32 grp_ctlds;
198 u32 grp_b1ds;
199 u32 grp_ddrhys;
200 u32 grp_ddrpke;
201 u32 grp_ddrmode;
202 u32 grp_ddr_type;
203};
204
205#define MX6SX_IOM_DDR_BASE 0x020e0200
206struct mx6sx_iomux_ddr_regs {
207 u32 res1[59];
208 u32 dram_dqm0;
209 u32 dram_dqm1;
210 u32 dram_dqm2;
211 u32 dram_dqm3;
212 u32 dram_ras;
213 u32 dram_cas;
214 u32 res2[2];
215 u32 dram_sdwe_b;
216 u32 dram_odt0;
217 u32 dram_odt1;
218 u32 dram_sdba0;
219 u32 dram_sdba1;
220 u32 dram_sdba2;
221 u32 dram_sdcke0;
222 u32 dram_sdcke1;
223 u32 dram_sdclk_0;
224 u32 dram_sdqs0;
225 u32 dram_sdqs1;
226 u32 dram_sdqs2;
227 u32 dram_sdqs3;
228 u32 dram_reset;
229};
230
231#define MX6SX_IOM_GRP_BASE 0x020e0500
232struct mx6sx_iomux_grp_regs {
233 u32 res1[61];
234 u32 grp_addds;
235 u32 grp_ddrmode_ctl;
236 u32 grp_ddrpke;
237 u32 grp_ddrpk;
238 u32 grp_ddrhys;
239 u32 grp_ddrmode;
240 u32 grp_b0ds;
241 u32 grp_b1ds;
242 u32 grp_ctlds;
243 u32 grp_ddr_type;
244 u32 grp_b2ds;
245 u32 grp_b3ds;
246};
247
248
249
250
251#define MX6DQ_IOM_DDR_BASE 0x020e0500
252struct mx6dq_iomux_ddr_regs {
253 u32 res1[3];
254 u32 dram_sdqs5;
255 u32 dram_dqm5;
256 u32 dram_dqm4;
257 u32 dram_sdqs4;
258 u32 dram_sdqs3;
259 u32 dram_dqm3;
260 u32 dram_sdqs2;
261 u32 dram_dqm2;
262 u32 res2[16];
263 u32 dram_cas;
264 u32 res3[2];
265 u32 dram_ras;
266 u32 dram_reset;
267 u32 res4[2];
268 u32 dram_sdclk_0;
269 u32 dram_sdba2;
270 u32 dram_sdcke0;
271 u32 dram_sdclk_1;
272 u32 dram_sdcke1;
273 u32 dram_sdodt0;
274 u32 dram_sdodt1;
275 u32 res5;
276 u32 dram_sdqs0;
277 u32 dram_dqm0;
278 u32 dram_sdqs1;
279 u32 dram_dqm1;
280 u32 dram_sdqs6;
281 u32 dram_dqm6;
282 u32 dram_sdqs7;
283 u32 dram_dqm7;
284};
285
286#define MX6DQ_IOM_GRP_BASE 0x020e0700
287struct mx6dq_iomux_grp_regs {
288 u32 res1[18];
289 u32 grp_b7ds;
290 u32 grp_addds;
291 u32 grp_ddrmode_ctl;
292 u32 res2;
293 u32 grp_ddrpke;
294 u32 res3[6];
295 u32 grp_ddrmode;
296 u32 res4[3];
297 u32 grp_b0ds;
298 u32 grp_b1ds;
299 u32 grp_ctlds;
300 u32 res5;
301 u32 grp_b2ds;
302 u32 grp_ddr_type;
303 u32 grp_b3ds;
304 u32 grp_b4ds;
305 u32 grp_b5ds;
306 u32 grp_b6ds;
307};
308
309#define MX6SDL_IOM_DDR_BASE 0x020e0400
310struct mx6sdl_iomux_ddr_regs {
311 u32 res1[25];
312 u32 dram_cas;
313 u32 res2[2];
314 u32 dram_dqm0;
315 u32 dram_dqm1;
316 u32 dram_dqm2;
317 u32 dram_dqm3;
318 u32 dram_dqm4;
319 u32 dram_dqm5;
320 u32 dram_dqm6;
321 u32 dram_dqm7;
322 u32 dram_ras;
323 u32 dram_reset;
324 u32 res3[2];
325 u32 dram_sdba2;
326 u32 dram_sdcke0;
327 u32 dram_sdcke1;
328 u32 dram_sdclk_0;
329 u32 dram_sdclk_1;
330 u32 dram_sdodt0;
331 u32 dram_sdodt1;
332 u32 dram_sdqs0;
333 u32 dram_sdqs1;
334 u32 dram_sdqs2;
335 u32 dram_sdqs3;
336 u32 dram_sdqs4;
337 u32 dram_sdqs5;
338 u32 dram_sdqs6;
339 u32 dram_sdqs7;
340};
341
342#define MX6SDL_IOM_GRP_BASE 0x020e0700
343struct mx6sdl_iomux_grp_regs {
344 u32 res1[18];
345 u32 grp_b7ds;
346 u32 grp_addds;
347 u32 grp_ddrmode_ctl;
348 u32 grp_ddrpke;
349 u32 res2[2];
350 u32 grp_ddrmode;
351 u32 grp_b0ds;
352 u32 res3;
353 u32 grp_ctlds;
354 u32 grp_b1ds;
355 u32 grp_ddr_type;
356 u32 grp_b2ds;
357 u32 grp_b3ds;
358 u32 grp_b4ds;
359 u32 grp_b5ds;
360 u32 res4;
361 u32 grp_b6ds;
362};
363
364
365struct mx6_ddr3_cfg {
366 u16 mem_speed;
367 u8 density;
368 u8 width;
369 u8 banks;
370 u8 rowaddr;
371 u8 coladdr;
372 u8 pagesz;
373 u16 trcd;
374 u16 trcmin;
375 u16 trasmin;
376 u8 SRT;
377};
378
379
380struct mx6_lpddr2_cfg {
381 u16 mem_speed;
382 u8 density;
383 u8 width;
384 u8 banks;
385 u8 rowaddr;
386 u8 coladdr;
387 u16 trcd_lp;
388 u16 trppb_lp;
389 u16 trpab_lp;
390 u16 trcmin;
391 u16 trasmin;
392};
393
394
395struct mx6_ddr_sysinfo {
396 u8 dsize;
397 u8 cs_density;
398 u8 ncs;
399 char cs1_mirror;
400 char bi_on;
401 u8 rtt_nom;
402 u8 rtt_wr;
403 u8 ralat;
404 u8 walat;
405 u8 mif3_mode;
406 u8 rst_to_cke;
407 u8 sde_to_rst;
408 u8 pd_fast_exit;
409 u8 ddr_type;
410 u8 refsel;
411 u8 refr;
412};
413
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420
421
422struct mx6_mmdc_calibration {
423
424 u32 p0_mpwldectrl0;
425 u32 p0_mpwldectrl1;
426 u32 p1_mpwldectrl0;
427 u32 p1_mpwldectrl1;
428
429 u32 p0_mpdgctrl0;
430 u32 p0_mpdgctrl1;
431 u32 p1_mpdgctrl0;
432 u32 p1_mpdgctrl1;
433
434 u32 p0_mprddlctl;
435 u32 p1_mprddlctl;
436
437 u32 p0_mpwrdlctl;
438 u32 p1_mpwrdlctl;
439
440 u32 mpzqlp2ctl;
441};
442
443
444void mx6dq_dram_iocfg(unsigned width,
445 const struct mx6dq_iomux_ddr_regs *,
446 const struct mx6dq_iomux_grp_regs *);
447void mx6sdl_dram_iocfg(unsigned width,
448 const struct mx6sdl_iomux_ddr_regs *,
449 const struct mx6sdl_iomux_grp_regs *);
450void mx6sx_dram_iocfg(unsigned width,
451 const struct mx6sx_iomux_ddr_regs *,
452 const struct mx6sx_iomux_grp_regs *);
453void mx6ul_dram_iocfg(unsigned width,
454 const struct mx6ul_iomux_ddr_regs *,
455 const struct mx6ul_iomux_grp_regs *);
456void mx6sl_dram_iocfg(unsigned width,
457 const struct mx6sl_iomux_ddr_regs *,
458 const struct mx6sl_iomux_grp_regs *);
459
460#if defined(CONFIG_MX6_DDRCAL)
461int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
462int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
463void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
464 struct mx6_mmdc_calibration *calib);
465#endif
466
467
468void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
469 const struct mx6_mmdc_calibration *,
470 const void *);
471
472#endif
473
474#define MX6_MMDC_P0_MDCTL 0x021b0000
475#define MX6_MMDC_P0_MDPDC 0x021b0004
476#define MX6_MMDC_P0_MDOTC 0x021b0008
477#define MX6_MMDC_P0_MDCFG0 0x021b000c
478#define MX6_MMDC_P0_MDCFG1 0x021b0010
479#define MX6_MMDC_P0_MDCFG2 0x021b0014
480#define MX6_MMDC_P0_MDMISC 0x021b0018
481#define MX6_MMDC_P0_MDSCR 0x021b001c
482#define MX6_MMDC_P0_MDREF 0x021b0020
483#define MX6_MMDC_P0_MDRWD 0x021b002c
484#define MX6_MMDC_P0_MDOR 0x021b0030
485#define MX6_MMDC_P0_MDASP 0x021b0040
486#define MX6_MMDC_P0_MAPSR 0x021b0404
487#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
488#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
489#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
490#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
491#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
492#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
493#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
494#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
495#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
496#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
497#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
498#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
499#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
500#define MX6_MMDC_P0_MPMUR0 0x021b08b8
501
502#define MX6_MMDC_P1_MDCTL 0x021b4000
503#define MX6_MMDC_P1_MDPDC 0x021b4004
504#define MX6_MMDC_P1_MDOTC 0x021b4008
505#define MX6_MMDC_P1_MDCFG0 0x021b400c
506#define MX6_MMDC_P1_MDCFG1 0x021b4010
507#define MX6_MMDC_P1_MDCFG2 0x021b4014
508#define MX6_MMDC_P1_MDMISC 0x021b4018
509#define MX6_MMDC_P1_MDSCR 0x021b401c
510#define MX6_MMDC_P1_MDREF 0x021b4020
511#define MX6_MMDC_P1_MDRWD 0x021b402c
512#define MX6_MMDC_P1_MDOR 0x021b4030
513#define MX6_MMDC_P1_MDASP 0x021b4040
514#define MX6_MMDC_P1_MAPSR 0x021b4404
515#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
516#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
517#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
518#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
519#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
520#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
521#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
522#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
523#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
524#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
525#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
526#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
527#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
528#define MX6_MMDC_P1_MPMUR0 0x021b48b8
529
530#endif
531