1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017 NXP 4 */ 5 6#ifndef __ASM_ARCH_MX8M_REGS_H__ 7#define __ASM_ARCH_MX8M_REGS_H__ 8 9#include <asm/mach-imx/regs-lcdif.h> 10 11#define ROM_VERSION_A0 0x800 12#define ROM_VERSION_B0 0x83C 13 14#define M4_BOOTROM_BASE_ADDR 0x007E0000 15 16#define SAI1_BASE_ADDR 0x30010000 17#define SAI6_BASE_ADDR 0x30030000 18#define SAI5_BASE_ADDR 0x30040000 19#define SAI4_BASE_ADDR 0x30050000 20#define SPBA2_BASE_ADDR 0x300F0000 21#define AIPS1_BASE_ADDR 0x301F0000 22#define GPIO1_BASE_ADDR 0X30200000 23#define GPIO2_BASE_ADDR 0x30210000 24#define GPIO3_BASE_ADDR 0x30220000 25#define GPIO4_BASE_ADDR 0x30230000 26#define GPIO5_BASE_ADDR 0x30240000 27#define ANA_TSENSOR_BASE_ADDR 0x30260000 28#define ANA_OSC_BASE_ADDR 0x30270000 29#define WDOG1_BASE_ADDR 0x30280000 30#define WDOG2_BASE_ADDR 0x30290000 31#define WDOG3_BASE_ADDR 0x302A0000 32#define SDMA2_BASE_ADDR 0x302C0000 33#define GPT1_BASE_ADDR 0x302D0000 34#define GPT2_BASE_ADDR 0x302E0000 35#define GPT3_BASE_ADDR 0x302F0000 36#define ROMCP_BASE_ADDR 0x30310000 37#define LCDIF_BASE_ADDR 0x30320000 38#define IOMUXC_BASE_ADDR 0x30330000 39#define IOMUXC_GPR_BASE_ADDR 0x30340000 40#define OCOTP_BASE_ADDR 0x30350000 41#define ANATOP_BASE_ADDR 0x30360000 42#define SNVS_HP_BASE_ADDR 0x30370000 43#define CCM_BASE_ADDR 0x30380000 44#define SRC_BASE_ADDR 0x30390000 45#define GPC_BASE_ADDR 0x303A0000 46#define SEMAPHORE1_BASE_ADDR 0x303B0000 47#define SEMAPHORE2_BASE_ADDR 0x303C0000 48#define RDC_BASE_ADDR 0x303D0000 49#define CSU_BASE_ADDR 0x303E0000 50 51#define AIPS2_BASE_ADDR 0x305F0000 52#define PWM1_BASE_ADDR 0x30660000 53#define PWM2_BASE_ADDR 0x30670000 54#define PWM3_BASE_ADDR 0x30680000 55#define PWM4_BASE_ADDR 0x30690000 56#define SYSCNT_RD_BASE_ADDR 0x306A0000 57#define SYSCNT_CMP_BASE_ADDR 0x306B0000 58#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 59#define GPT6_BASE_ADDR 0x306E0000 60#define GPT5_BASE_ADDR 0x306F0000 61#define GPT4_BASE_ADDR 0x30700000 62#define PERFMON1_BASE_ADDR 0x307C0000 63#define PERFMON2_BASE_ADDR 0x307D0000 64#define QOSC_BASE_ADDR 0x307F0000 65 66#define SPDIF1_BASE_ADDR 0x30810000 67#define ECSPI1_BASE_ADDR 0x30820000 68#define ECSPI2_BASE_ADDR 0x30830000 69#define ECSPI3_BASE_ADDR 0x30840000 70#define UART1_BASE_ADDR 0x30860000 71#define UART3_BASE_ADDR 0x30880000 72#define UART2_BASE_ADDR 0x30890000 73#define SPDIF2_BASE_ADDR 0x308A0000 74#define SAI2_BASE_ADDR 0x308B0000 75#define SAI3_BASE_ADDR 0x308C0000 76#define SPBA1_BASE_ADDR 0x308F0000 77#define CAAM_BASE_ADDR 0x30900000 78#define AIPS3_BASE_ADDR 0x309F0000 79#define MIPI_PHY_BASE_ADDR 0x30A00000 80#define MIPI_DSI_BASE_ADDR 0x30A10000 81#define I2C1_BASE_ADDR 0x30A20000 82#define I2C2_BASE_ADDR 0x30A30000 83#define I2C3_BASE_ADDR 0x30A40000 84#define I2C4_BASE_ADDR 0x30A50000 85#define UART4_BASE_ADDR 0x30A60000 86#define MIPI_CSI_BASE_ADDR 0x30A70000 87#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 88#define CSI1_BASE_ADDR 0x30A90000 89#define MU_A_BASE_ADDR 0x30AA0000 90#define MU_B_BASE_ADDR 0x30AB0000 91#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 92#define USDHC1_BASE_ADDR 0x30B40000 93#define USDHC2_BASE_ADDR 0x30B50000 94#define MIPI_CS2_BASE_ADDR 0x30B60000 95#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 96#define CSI2_BASE_ADDR 0x30B80000 97#define QSPI0_BASE_ADDR 0x30BB0000 98#define QSPI0_AMBA_BASE 0x08000000 99#define SDMA1_BASE_ADDR 0x30BD0000 100#define ENET1_BASE_ADDR 0x30BE0000 101 102#define HDMI_CTRL_BASE_ADDR 0x32C00000 103#define AIPS4_BASE_ADDR 0x32DF0000 104#define DC1_BASE_ADDR 0x32E00000 105#define DC2_BASE_ADDR 0x32E10000 106#define DC3_BASE_ADDR 0x32E20000 107#define HDMI_SEC_BASE_ADDR 0x32E40000 108#define TZASC_BASE_ADDR 0x32F80000 109#define MTR_BASE_ADDR 0x32FB0000 110#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000 111 112#define MXS_APBH_BASE 0x33000000 113#define MXS_GPMI_BASE 0x33002000 114#define MXS_BCH_BASE 0x33004000 115 116#define USB1_BASE_ADDR 0x38100000 117#define USB2_BASE_ADDR 0x38200000 118#define USB1_PHY_BASE_ADDR 0x381F0000 119#define USB2_PHY_BASE_ADDR 0x382F0000 120 121#define MXS_LCDIF_BASE LCDIF_BASE_ADDR 122 123#define SRC_IPS_BASE_ADDR 0x30390000 124#define SRC_DDRC_RCR_ADDR 0x30391000 125#define SRC_DDRC2_RCR_ADDR 0x30391004 126 127#define DDRC_DDR_SS_GPR0 0x3d000000 128#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) 129#define DDR_CSD1_BASE_ADDR 0x40000000 130 131#if !defined(__ASSEMBLY__) 132#include <asm/types.h> 133#include <linux/bitops.h> 134#include <stdbool.h> 135 136#define GPR_TZASC_EN BIT(0) 137#define GPR_TZASC_EN_LOCK BIT(16) 138 139#define SRC_SCR_M4_ENABLE_OFFSET 3 140#define SRC_SCR_M4_ENABLE_MASK BIT(3) 141#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 142#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) 143#define SRC_DDR1_ENABLE_MASK 0x8F000000UL 144#define SRC_DDR2_ENABLE_MASK 0x8F000000UL 145#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) 146#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) 147#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) 148#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) 149 150struct iomuxc_gpr_base_regs { 151 u32 gpr[47]; 152}; 153 154struct ocotp_regs { 155 u32 ctrl; 156 u32 ctrl_set; 157 u32 ctrl_clr; 158 u32 ctrl_tog; 159 u32 timing; 160 u32 rsvd0[3]; 161 u32 data; 162 u32 rsvd1[3]; 163 u32 read_ctrl; 164 u32 rsvd2[3]; 165 u32 read_fuse_data; 166 u32 rsvd3[3]; 167 u32 sw_sticky; 168 u32 rsvd4[3]; 169 u32 scs; 170 u32 scs_set; 171 u32 scs_clr; 172 u32 scs_tog; 173 u32 crc_addr; 174 u32 rsvd5[3]; 175 u32 crc_value; 176 u32 rsvd6[3]; 177 u32 version; 178 u32 rsvd7[0xdb]; 179 180 /* fuse banks */ 181 struct fuse_bank { 182 u32 fuse_regs[0x10]; 183 } bank[0]; 184}; 185 186struct fuse_bank0_regs { 187 u32 lock; 188 u32 rsvd0[3]; 189 u32 uid_low; 190 u32 rsvd1[3]; 191 u32 uid_high; 192 u32 rsvd2[7]; 193}; 194 195struct fuse_bank1_regs { 196 u32 tester3; 197 u32 rsvd0[3]; 198 u32 tester4; 199 u32 rsvd1[3]; 200 u32 tester5; 201 u32 rsvd2[3]; 202 u32 cfg0; 203 u32 rsvd3[3]; 204}; 205 206struct anamix_pll { 207 u32 audio_pll1_cfg0; 208 u32 audio_pll1_cfg1; 209 u32 audio_pll2_cfg0; 210 u32 audio_pll2_cfg1; 211 u32 video_pll_cfg0; 212 u32 video_pll_cfg1; 213 u32 gpu_pll_cfg0; 214 u32 gpu_pll_cfg1; 215 u32 vpu_pll_cfg0; 216 u32 vpu_pll_cfg1; 217 u32 arm_pll_cfg0; 218 u32 arm_pll_cfg1; 219 u32 sys_pll1_cfg0; 220 u32 sys_pll1_cfg1; 221 u32 sys_pll1_cfg2; 222 u32 sys_pll2_cfg0; 223 u32 sys_pll2_cfg1; 224 u32 sys_pll2_cfg2; 225 u32 sys_pll3_cfg0; 226 u32 sys_pll3_cfg1; 227 u32 sys_pll3_cfg2; 228 u32 video_pll2_cfg0; 229 u32 video_pll2_cfg1; 230 u32 video_pll2_cfg2; 231 u32 dram_pll_cfg0; 232 u32 dram_pll_cfg1; 233 u32 dram_pll_cfg2; 234 u32 digprog; 235 u32 osc_misc_cfg; 236 u32 pllout_monitor_cfg; 237 u32 frac_pllout_div_cfg; 238 u32 sscg_pllout_div_cfg; 239}; 240 241struct fuse_bank9_regs { 242 u32 mac_addr0; 243 u32 rsvd0[3]; 244 u32 mac_addr1; 245 u32 rsvd1[11]; 246}; 247 248/* System Reset Controller (SRC) */ 249struct src { 250 u32 scr; 251 u32 a53rcr; 252 u32 a53rcr1; 253 u32 m4rcr; 254 u32 reserved1[4]; 255 u32 usbophy1_rcr; 256 u32 usbophy2_rcr; 257 u32 mipiphy_rcr; 258 u32 pciephy_rcr; 259 u32 hdmi_rcr; 260 u32 disp_rcr; 261 u32 reserved2[2]; 262 u32 gpu_rcr; 263 u32 vpu_rcr; 264 u32 pcie2_rcr; 265 u32 mipiphy1_rcr; 266 u32 mipiphy2_rcr; 267 u32 reserved3; 268 u32 sbmr1; 269 u32 srsr; 270 u32 reserved4[2]; 271 u32 sisr; 272 u32 simr; 273 u32 sbmr2; 274 u32 gpr1; 275 u32 gpr2; 276 u32 gpr3; 277 u32 gpr4; 278 u32 gpr5; 279 u32 gpr6; 280 u32 gpr7; 281 u32 gpr8; 282 u32 gpr9; 283 u32 gpr10; 284 u32 reserved5[985]; 285 u32 ddr1_rcr; 286 u32 ddr2_rcr; 287}; 288 289struct gpc_reg { 290 u32 lpcr_bsc; 291 u32 lpcr_ad; 292 u32 lpcr_cpu1; 293 u32 lpcr_cpu2; 294 u32 lpcr_cpu3; 295 u32 slpcr; 296 u32 mst_cpu_mapping; 297 u32 mmdc_cpu_mapping; 298 u32 mlpcr; 299 u32 pgc_ack_sel; 300 u32 pgc_ack_sel_m4; 301 u32 gpc_misc; 302 u32 imr1_core0; 303 u32 imr2_core0; 304 u32 imr3_core0; 305 u32 imr4_core0; 306 u32 imr1_core1; 307 u32 imr2_core1; 308 u32 imr3_core1; 309 u32 imr4_core1; 310 u32 imr1_cpu1; 311 u32 imr2_cpu1; 312 u32 imr3_cpu1; 313 u32 imr4_cpu1; 314 u32 imr1_cpu3; 315 u32 imr2_cpu3; 316 u32 imr3_cpu3; 317 u32 imr4_cpu3; 318 u32 isr1_cpu0; 319 u32 isr2_cpu0; 320 u32 isr3_cpu0; 321 u32 isr4_cpu0; 322 u32 isr1_cpu1; 323 u32 isr2_cpu1; 324 u32 isr3_cpu1; 325 u32 isr4_cpu1; 326 u32 isr1_cpu2; 327 u32 isr2_cpu2; 328 u32 isr3_cpu2; 329 u32 isr4_cpu2; 330 u32 isr1_cpu3; 331 u32 isr2_cpu3; 332 u32 isr3_cpu3; 333 u32 isr4_cpu3; 334 u32 slt0_cfg; 335 u32 slt1_cfg; 336 u32 slt2_cfg; 337 u32 slt3_cfg; 338 u32 slt4_cfg; 339 u32 slt5_cfg; 340 u32 slt6_cfg; 341 u32 slt7_cfg; 342 u32 slt8_cfg; 343 u32 slt9_cfg; 344 u32 slt10_cfg; 345 u32 slt11_cfg; 346 u32 slt12_cfg; 347 u32 slt13_cfg; 348 u32 slt14_cfg; 349 u32 pgc_cpu_0_1_mapping; 350 u32 cpu_pgc_up_trg; 351 u32 mix_pgc_up_trg; 352 u32 pu_pgc_up_trg; 353 u32 cpu_pgc_dn_trg; 354 u32 mix_pgc_dn_trg; 355 u32 pu_pgc_dn_trg; 356 u32 lpcr_bsc2; 357 u32 pgc_cpu_2_3_mapping; 358 u32 lps_cpu0; 359 u32 lps_cpu1; 360 u32 lps_cpu2; 361 u32 lps_cpu3; 362 u32 gpc_gpr; 363 u32 gtor; 364 u32 debug_addr1; 365 u32 debug_addr2; 366 u32 cpu_pgc_up_status1; 367 u32 mix_pgc_up_status0; 368 u32 mix_pgc_up_status1; 369 u32 mix_pgc_up_status2; 370 u32 m4_mix_pgc_up_status0; 371 u32 m4_mix_pgc_up_status1; 372 u32 m4_mix_pgc_up_status2; 373 u32 pu_pgc_up_status0; 374 u32 pu_pgc_up_status1; 375 u32 pu_pgc_up_status2; 376 u32 m4_pu_pgc_up_status0; 377 u32 m4_pu_pgc_up_status1; 378 u32 m4_pu_pgc_up_status2; 379 u32 a53_lp_io_0; 380 u32 a53_lp_io_1; 381 u32 a53_lp_io_2; 382 u32 cpu_pgc_dn_status1; 383 u32 mix_pgc_dn_status0; 384 u32 mix_pgc_dn_status1; 385 u32 mix_pgc_dn_status2; 386 u32 m4_mix_pgc_dn_status0; 387 u32 m4_mix_pgc_dn_status1; 388 u32 m4_mix_pgc_dn_status2; 389 u32 pu_pgc_dn_status0; 390 u32 pu_pgc_dn_status1; 391 u32 pu_pgc_dn_status2; 392 u32 m4_pu_pgc_dn_status0; 393 u32 m4_pu_pgc_dn_status1; 394 u32 m4_pu_pgc_dn_status2; 395 u32 res[3]; 396 u32 mix_pdn_flg; 397 u32 pu_pdn_flg; 398 u32 m4_mix_pdn_flg; 399 u32 m4_pu_pdn_flg; 400 u32 imr1_core2; 401 u32 imr2_core2; 402 u32 imr3_core2; 403 u32 imr4_core2; 404 u32 imr1_core3; 405 u32 imr2_core3; 406 u32 imr3_core3; 407 u32 imr4_core3; 408 u32 pgc_ack_sel_pu; 409 u32 pgc_ack_sel_m4_pu; 410 u32 slt15_cfg; 411 u32 slt16_cfg; 412 u32 slt17_cfg; 413 u32 slt18_cfg; 414 u32 slt19_cfg; 415 u32 gpc_pu_pwrhsk; 416 u32 slt0_cfg_pu; 417 u32 slt1_cfg_pu; 418 u32 slt2_cfg_pu; 419 u32 slt3_cfg_pu; 420 u32 slt4_cfg_pu; 421 u32 slt5_cfg_pu; 422 u32 slt6_cfg_pu; 423 u32 slt7_cfg_pu; 424 u32 slt8_cfg_pu; 425 u32 slt9_cfg_pu; 426 u32 slt10_cfg_pu; 427 u32 slt11_cfg_pu; 428 u32 slt12_cfg_pu; 429 u32 slt13_cfg_pu; 430 u32 slt14_cfg_pu; 431 u32 slt15_cfg_pu; 432 u32 slt16_cfg_pu; 433 u32 slt17_cfg_pu; 434 u32 slt18_cfg_pu; 435 u32 slt19_cfg_pu; 436}; 437 438#define WDOG_WDT_MASK BIT(3) 439#define WDOG_WDZST_MASK BIT(0) 440struct wdog_regs { 441 u16 wcr; /* Control */ 442 u16 wsr; /* Service */ 443 u16 wrsr; /* Reset Status */ 444 u16 wicr; /* Interrupt Control */ 445 u16 wmcr; /* Miscellaneous Control */ 446}; 447 448struct bootrom_sw_info { 449 u8 reserved_1; 450 u8 boot_dev_instance; 451 u8 boot_dev_type; 452 u8 reserved_2; 453 u32 core_freq; 454 u32 axi_freq; 455 u32 ddr_freq; 456 u32 tick_freq; 457 u32 reserved_3[3]; 458}; 459 460#define ROM_SW_INFO_ADDR_B0 0x00000968 461#define ROM_SW_INFO_ADDR_A0 0x000009e8 462 463#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ 464 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ 465 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 466#endif 467#endif 468