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5
6#include <common.h>
7#include <asm/mmu.h>
8#include <asm/immap_85xx.h>
9#include <asm/processor.h>
10#include <fsl_ddr_sdram.h>
11#include <fsl_ddr_dimm_params.h>
12#include <asm/io.h>
13#include <asm/fsl_law.h>
14
15#ifndef CONFIG_SYS_DDR_RAW_TIMING
16#define CONFIG_SYS_DRAM_SIZE 1024
17
18fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
19 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
20 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
21 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
22 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
23 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
24 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
25 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
26 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
27 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
28 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
29 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
30 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
31 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
32 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
33 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
34 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
35 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
36 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
37 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
38 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
39 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
40 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
41 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
42 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
43};
44
45fixed_ddr_parm_t fixed_ddr_parm_0[] = {
46 {750, 850, &ddr_cfg_regs_800},
47 {0, 0, NULL}
48};
49
50unsigned long get_sdram_size(void)
51{
52 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
53}
54
55
56
57
58phys_size_t fixed_sdram(void)
59{
60 int i;
61 char buf[32];
62 fsl_ddr_cfg_regs_t ddr_cfg_regs;
63 phys_size_t ddr_size;
64 ulong ddr_freq, ddr_freq_mhz;
65
66 ddr_freq = get_ddr_freq(0);
67 ddr_freq_mhz = ddr_freq / 1000000;
68
69 printf("Configuring DDR for %s MT/s data rate\n",
70 strmhz(buf, ddr_freq));
71
72 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
73 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
74 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
75 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
76 sizeof(ddr_cfg_regs));
77 break;
78 }
79 }
80
81 if (fixed_ddr_parm_0[i].max_freq == 0) {
82 panic("Unsupported DDR data rate %s MT/s data rate\n",
83 strmhz(buf, ddr_freq));
84 }
85
86 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
87 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
88
89 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
90 LAW_TRGT_IF_DDR_1) < 0) {
91 printf("ERROR setting Local Access Windows for DDR\n");
92 return 0;
93 }
94
95 return ddr_size;
96}
97
98#else
99
100dimm_params_t ddr_raw_timing = {
101 .n_ranks = 1,
102 .rank_density = 1073741824u,
103 .capacity = 1073741824u,
104 .primary_sdram_width = 32,
105 .ec_sdram_width = 0,
106 .registered_dimm = 0,
107 .mirrored_dimm = 0,
108 .n_row_addr = 15,
109 .n_col_addr = 10,
110 .n_banks_per_sdram_device = 8,
111 .edc_config = 0,
112 .burst_lengths_bitmask = 0x0c,
113
114 .tckmin_x_ps = 1870,
115 .caslat_x = 0x1e << 4,
116 .taa_ps = 13125,
117 .twr_ps = 15000,
118 .trcd_ps = 13125,
119 .trrd_ps = 7500,
120 .trp_ps = 13125,
121 .tras_ps = 37500,
122 .trc_ps = 50625,
123 .trfc_ps = 160000,
124 .twtr_ps = 7500,
125 .trtp_ps = 7500,
126 .refresh_rate_ps = 7800000,
127 .tfaw_ps = 37500,
128};
129
130int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
131 unsigned int controller_number,
132 unsigned int dimm_number)
133{
134 const char dimm_model[] = "Fixed DDR on board";
135
136 if ((controller_number == 0) && (dimm_number == 0)) {
137 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
138 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
139 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
140 }
141
142 return 0;
143}
144
145void fsl_ddr_board_options(memctl_options_t *popts,
146 dimm_params_t *pdimm,
147 unsigned int ctrl_num)
148{
149 int i;
150 popts->clk_adjust = 6;
151 popts->cpo_override = 0x1f;
152 popts->write_data_delay = 2;
153 popts->half_strength_driver_enable = 1;
154
155 popts->wrlvl_en = 1;
156 popts->wrlvl_override = 1;
157 popts->wrlvl_sample = 0xf;
158 popts->wrlvl_start = 0x8;
159 popts->trwt_override = 1;
160 popts->trwt = 0;
161
162 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
163 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
164 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
165 }
166}
167
168#endif
169
