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6#include <common.h>
7#include <command.h>
8#include <pci.h>
9#include <asm/processor.h>
10#include <asm/mmu.h>
11#include <asm/cache.h>
12#include <asm/immap_85xx.h>
13#include <asm/fsl_pci.h>
14#include <fsl_ddr_sdram.h>
15#include <asm/io.h>
16#include <asm/fsl_serdes.h>
17#include <miiphy.h>
18#include <linux/libfdt.h>
19#include <fdt_support.h>
20#include <tsec.h>
21#include <fsl_mdio.h>
22#include <netdev.h>
23
24#include "../common/sgmii_riser.h"
25
26int checkboard (void)
27{
28 u8 vboot;
29 u8 *pixis_base = (u8 *)PIXIS_BASE;
30
31 printf("Board: MPC8572DS Sys ID: 0x%02x, "
32 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
33 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
34 in_8(pixis_base + PIXIS_PVER));
35
36 vboot = in_8(pixis_base + PIXIS_VBOOT);
37 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
38 case PIXIS_VBOOT_LBMAP_NOR0:
39 puts ("vBank: 0\n");
40 break;
41 case PIXIS_VBOOT_LBMAP_PJET:
42 puts ("Promjet\n");
43 break;
44 case PIXIS_VBOOT_LBMAP_NAND:
45 puts ("NAND\n");
46 break;
47 case PIXIS_VBOOT_LBMAP_NOR1:
48 puts ("vBank: 1\n");
49 break;
50 }
51
52 return 0;
53}
54
55
56#if !defined(CONFIG_SPD_EEPROM)
57
58
59
60
61phys_size_t fixed_sdram (void)
62{
63 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
64 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
65 uint d_init;
66
67 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
68 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
69
70 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
71 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
72 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
73 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
74 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
75 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
76 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
77 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
78 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
79 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
80
81#if defined (CONFIG_DDR_ECC)
82 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
83 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
84 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
85#endif
86 asm("sync;isync");
87
88 udelay(500);
89
90 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
91
92#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
93 d_init = 1;
94 debug("DDR - 1st controller: memory initializing\n");
95
96
97
98
99 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
100 udelay(1000);
101 }
102 debug("DDR: memory initialized\n\n");
103 asm("sync; isync");
104 udelay(500);
105#endif
106
107 return 512 * 1024 * 1024;
108}
109
110#endif
111
112#ifdef CONFIG_PCI
113void pci_init_board(void)
114{
115 struct pci_controller *hose;
116
117 fsl_pcie_init_board(0);
118
119 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
120
121 if (hose) {
122 u32 temp32;
123 u8 uli_busno = hose->first_busno + 2;
124
125
126
127
128
129
130 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
131 PCI_BASE_ADDRESS_1, &temp32);
132
133 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
134 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
135 temp32, 4, 0);
136 debug(" uli1572 read to %p\n", p);
137 in_be32(p);
138 }
139 }
140}
141#endif
142
143int board_early_init_r(void)
144{
145 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
146 int flash_esel = find_tlb_idx((void *)flashbase, 1);
147
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150
151
152
153
154 flush_dcache();
155 invalidate_icache();
156
157 if (flash_esel == -1) {
158
159 puts("Error: Could not find TLB for FLASH BASE\n");
160 flash_esel = 2;
161 } else {
162
163 disable_tlb(flash_esel);
164 }
165
166 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
167 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
168 0, flash_esel, BOOKE_PAGESZ_256M, 1);
169
170 return 0;
171}
172
173int board_eth_init(bd_t *bis)
174{
175#ifdef CONFIG_TSEC_ENET
176 struct fsl_pq_mdio_info mdio_info;
177 struct tsec_info_struct tsec_info[4];
178 int num = 0;
179
180#ifdef CONFIG_TSEC1
181 SET_STD_TSEC_INFO(tsec_info[num], 1);
182 if (is_serdes_configured(SGMII_TSEC1)) {
183 puts("eTSEC1 is in sgmii mode.\n");
184 tsec_info[num].flags |= TSEC_SGMII;
185 }
186 num++;
187#endif
188#ifdef CONFIG_TSEC2
189 SET_STD_TSEC_INFO(tsec_info[num], 2);
190 if (is_serdes_configured(SGMII_TSEC2)) {
191 puts("eTSEC2 is in sgmii mode.\n");
192 tsec_info[num].flags |= TSEC_SGMII;
193 }
194 num++;
195#endif
196#ifdef CONFIG_TSEC3
197 SET_STD_TSEC_INFO(tsec_info[num], 3);
198 if (is_serdes_configured(SGMII_TSEC3)) {
199 puts("eTSEC3 is in sgmii mode.\n");
200 tsec_info[num].flags |= TSEC_SGMII;
201 }
202 num++;
203#endif
204#ifdef CONFIG_TSEC4
205 SET_STD_TSEC_INFO(tsec_info[num], 4);
206 if (is_serdes_configured(SGMII_TSEC4)) {
207 puts("eTSEC4 is in sgmii mode.\n");
208 tsec_info[num].flags |= TSEC_SGMII;
209 }
210 num++;
211#endif
212
213 if (!num) {
214 printf("No TSECs initialized\n");
215
216 return 0;
217 }
218
219#ifdef CONFIG_FSL_SGMII_RISER
220 fsl_sgmii_riser_init(tsec_info, num);
221#endif
222
223 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
224 mdio_info.name = DEFAULT_MII_NAME;
225 fsl_pq_mdio_init(bis, &mdio_info);
226
227 tsec_eth_init(bis, tsec_info, num);
228#endif
229
230 return pci_eth_init(bis);
231}
232
233#if defined(CONFIG_OF_BOARD_SETUP)
234int ft_board_setup(void *blob, bd_t *bd)
235{
236 phys_addr_t base;
237 phys_size_t size;
238
239 ft_cpu_setup(blob, bd);
240
241 base = env_get_bootm_low();
242 size = env_get_bootm_size();
243
244 fdt_fixup_memory(blob, (u64)base, (u64)size);
245
246 FT_FSL_PCI_SETUP;
247
248#ifdef CONFIG_FSL_SGMII_RISER
249 fsl_sgmii_riser_fdt_fixup(blob);
250#endif
251
252 return 0;
253}
254#endif
255
