LXR uboot/board/freescale/mpc8610hpcd/mpc8610hpcd.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <command.h>
   8#include <pci.h>
   9#include <asm/processor.h>
  10#include <asm/immap_86xx.h>
  11#include <asm/fsl_pci.h>
  12#include <fsl_ddr_sdram.h>
  13#include <asm/fsl_serdes.h>
  14#include <i2c.h>
  15#include <asm/io.h>
  16#include <linux/libfdt.h>
  17#include <fdt_support.h>
  18#include <spd_sdram.h>
  19#include <netdev.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23void sdram_init(void);
  24phys_size_t fixed_sdram(void);
  25int mpc8610hpcd_diu_init(void);
  26
  27
  28/* called before any console output */
  29int board_early_init_f(void)
  30{
  31        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  32        volatile ccsr_gur_t *gur = &immap->im_gur;
  33
  34        gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  35
  36        return 0;
  37}
  38
  39int misc_init_r(void)
  40{
  41        u8 tmp_val, version;
  42        u8 *pixis_base = (u8 *)PIXIS_BASE;
  43
  44        /*Do not use 8259PIC*/
  45        tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  46        out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
  47
  48        /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  49        version = in_8(pixis_base + PIXIS_PVER);
  50        if(version >= 0x07) {
  51                tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  52                out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
  53        }
  54
  55        /* Using this for DIU init before the driver in linux takes over
  56         *  Enable the TFP410 Encoder (I2C address 0x38)
  57         */
  58
  59        tmp_val = 0xBF;
  60        i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  61        /* Verify if enabled */
  62        tmp_val = 0;
  63        i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  64        debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  65
  66        tmp_val = 0x10;
  67        i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  68        /* Verify if enabled */
  69        tmp_val = 0;
  70        i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  71        debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  72
  73        return 0;
  74}
  75
  76int checkboard(void)
  77{
  78        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  79        volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  80        u8 *pixis_base = (u8 *)PIXIS_BASE;
  81
  82        printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
  83                "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  84                in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  85                in_8(pixis_base + PIXIS_PVER));
  86
  87        /*
  88         * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
  89         * bank and LBMAP=00 is the alternate bank.  However, the pixis
  90         * altbank code can only set bits, not clear them, so we treat 00 as
  91         * the normal bank and 11 as the alternate.
  92         */
  93        switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
  94        case 0:
  95                puts("vBank: Standard\n");
  96                break;
  97        case 0x40:
  98                puts("Promjet\n");
  99                break;
 100        case 0x80:
 101                puts("NAND\n");
 102                break;
 103        case 0xC0:
 104                puts("vBank: Alternate\n");
 105                break;
 106        }
 107
 108        mcm->abcr |= 0x00010000; /* 0 */
 109        mcm->hpmr3 = 0x80000008; /* 4c */
 110        mcm->hpmr0 = 0;
 111        mcm->hpmr1 = 0;
 112        mcm->hpmr2 = 0;
 113        mcm->hpmr4 = 0;
 114        mcm->hpmr5 = 0;
 115
 116        return 0;
 117}
 118
 119
 120int dram_init(void)
 121{
 122        phys_size_t dram_size = 0;
 123
 124#if defined(CONFIG_SPD_EEPROM)
 125        dram_size = fsl_ddr_sdram();
 126#else
 127        dram_size = fixed_sdram();
 128#endif
 129
 130        setup_ddr_bat(dram_size);
 131
 132        debug(" DDR: ");
 133        gd->ram_size = dram_size;
 134
 135        return 0;
 136}
 137
 138
 139#if !defined(CONFIG_SPD_EEPROM)
 140/*
 141 * Fixed sdram init -- doesn't use serial presence detect.
 142 */
 143
 144phys_size_t fixed_sdram(void)
 145{
 146#if !defined(CONFIG_SYS_RAMBOOT)
 147        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 148        struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
 149        uint d_init;
 150
 151        ddr->cs0_bnds = 0x0000001f;
 152        ddr->cs0_config = 0x80010202;
 153
 154        ddr->timing_cfg_3 = 0x00000000;
 155        ddr->timing_cfg_0 = 0x00260802;
 156        ddr->timing_cfg_1 = 0x3935d322;
 157        ddr->timing_cfg_2 = 0x14904cc8;
 158        ddr->sdram_mode = 0x00480432;
 159        ddr->sdram_mode_2 = 0x00000000;
 160        ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 161        ddr->sdram_data_init = 0xDEADBEEF;
 162        ddr->sdram_clk_cntl = 0x03800000;
 163        ddr->sdram_cfg_2 = 0x04400010;
 164
 165#if defined(CONFIG_DDR_ECC)
 166        ddr->err_int_en = 0x0000000d;
 167        ddr->err_disable = 0x00000000;
 168        ddr->err_sbe = 0x00010000;
 169#endif
 170        asm("sync;isync");
 171
 172        udelay(500);
 173
 174        ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
 175
 176
 177#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 178        d_init = 1;
 179        debug("DDR - 1st controller: memory initializing\n");
 180        /*
 181         * Poll until memory is initialized.
 182         * 512 Meg at 400 might hit this 200 times or so.
 183         */
 184        while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 185                udelay(1000);
 186
 187        debug("DDR: memory initialized\n\n");
 188        asm("sync; isync");
 189        udelay(500);
 190#endif
 191
 192        return 512 * 1024 * 1024;
 193#endif
 194        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 195}
 196
 197#endif
 198
 199#if defined(CONFIG_PCI)
 200/*
 201 * Initialize PCI Devices, report devices found.
 202 */
 203
 204#ifndef CONFIG_PCI_PNP
 205static struct pci_config_table pci_fsl86xxads_config_table[] = {
 206        {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 207         PCI_IDSEL_NUMBER, PCI_ANY_ID,
 208         pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 209                                 PCI_ENET0_MEMADDR,
 210                                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
 211        {}
 212};
 213#endif
 214
 215
 216static struct pci_controller pci1_hose;
 217#endif /* CONFIG_PCI */
 218
 219void pci_init_board(void)
 220{
 221        volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 222        volatile ccsr_gur_t *gur = &immap->im_gur;
 223        struct fsl_pci_info pci_info;
 224        u32 devdisr;
 225        int first_free_busno;
 226        int pci_agent;
 227
 228        devdisr = in_be32(&gur->devdisr);
 229
 230        first_free_busno = fsl_pcie_init_board(0);
 231
 232#ifdef CONFIG_PCI1
 233        if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
 234                SET_STD_PCI_INFO(pci_info, 1);
 235                set_next_law(pci_info.mem_phys,
 236                        law_size_bits(pci_info.mem_size), pci_info.law);
 237                set_next_law(pci_info.io_phys,
 238                        law_size_bits(pci_info.io_size), pci_info.law);
 239
 240                pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 241                printf("PCI: connected to PCI slots as %s" \
 242                        " (base address %lx)\n",
 243                        pci_agent ? "Agent" : "Host",
 244                        pci_info.regs);
 245#ifndef CONFIG_PCI_PNP
 246                pci1_hose.config_table = pci_mpc86xxcts_config_table;
 247#endif
 248                first_free_busno = fsl_pci_init_port(&pci_info,
 249                                        &pci1_hose, first_free_busno);
 250        } else {
 251                printf("PCI: disabled\n");
 252        }
 253
 254        puts("\n");
 255#else
 256        setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
 257#endif
 258
 259        fsl_pcie_init_board(first_free_busno);
 260}
 261
 262#if defined(CONFIG_OF_BOARD_SETUP)
 263int ft_board_setup(void *blob, bd_t *bd)
 264{
 265        ft_cpu_setup(blob, bd);
 266
 267        FT_FSL_PCI_SETUP;
 268
 269        return 0;
 270}
 271#endif
 272
 273/*
 274 * get_board_sys_clk
 275 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 276 */
 277
 278unsigned long
 279get_board_sys_clk(ulong dummy)
 280{
 281        u8 i;
 282        ulong val = 0;
 283        u8 *pixis_base = (u8 *)PIXIS_BASE;
 284
 285        i = in_8(pixis_base + PIXIS_SPD);
 286        i &= 0x07;
 287
 288        switch (i) {
 289        case 0:
 290                val = 33333000;
 291                break;
 292        case 1:
 293                val = 39999600;
 294                break;
 295        case 2:
 296                val = 49999500;
 297                break;
 298        case 3:
 299                val = 66666000;
 300                break;
 301        case 4:
 302                val = 83332500;
 303                break;
 304        case 5:
 305                val = 99999000;
 306                break;
 307        case 6:
 308                val = 133332000;
 309                break;
 310        case 7:
 311                val = 166665000;
 312                break;
 313        }
 314
 315        return val;
 316}
 317
 318int board_eth_init(bd_t *bis)
 319{
 320        return pci_eth_init(bis);
 321}
 322
 323void board_reset(void)
 324{
 325        u8 *pixis_base = (u8 *)PIXIS_BASE;
 326
 327        out_8(pixis_base + PIXIS_RST, 0);
 328
 329        while (1)
 330                ;
 331}
 332