LXR uboot/drivers/i2c/davinci

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * TI DaVinci (TMS320DM644x) I2C driver.
   4 *
   5 * (C) Copyright 2012-2014
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
   8 * --------------------------------------------------------
   9 *
  10 * NOTE: This driver should be converted to driver model before June 2017.
  11 * Please see doc/driver-model/i2c-howto.txt for instructions.
  12 */
  13
  14#include <common.h>
  15#include <i2c.h>
  16#include <dm.h>
  17#include <asm/arch/hardware.h>
  18#include <asm/arch/i2c_defs.h>
  19#include <asm/io.h>
  20#include "davinci_i2c.h"
  21
  22#ifdef CONFIG_DM_I2C
  23/* Information about i2c controller */
  24struct i2c_bus {
  25        int                     id;
  26        uint                    speed;
  27        struct i2c_regs         *regs;
  28};
  29#endif
  30
  31#define CHECK_NACK() \
  32        do {\
  33                if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  34                        REG(&(i2c_base->i2c_con)) = 0;\
  35                        return 1;\
  36                } \
  37        } while (0)
  38
  39static int _wait_for_bus(struct i2c_regs *i2c_base)
  40{
  41        int     stat, timeout;
  42
  43        REG(&(i2c_base->i2c_stat)) = 0xffff;
  44
  45        for (timeout = 0; timeout < 10; timeout++) {
  46                stat = REG(&(i2c_base->i2c_stat));
  47                if (!((stat) & I2C_STAT_BB)) {
  48                        REG(&(i2c_base->i2c_stat)) = 0xffff;
  49                        return 0;
  50                }
  51
  52                REG(&(i2c_base->i2c_stat)) = stat;
  53                udelay(50000);
  54        }
  55
  56        REG(&(i2c_base->i2c_stat)) = 0xffff;
  57        return 1;
  58}
  59
  60static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
  61{
  62        int     stat, timeout;
  63
  64        for (timeout = 0; timeout < 10; timeout++) {
  65                udelay(1000);
  66                stat = REG(&(i2c_base->i2c_stat));
  67                if (stat & mask)
  68                        return stat;
  69        }
  70
  71        REG(&(i2c_base->i2c_stat)) = 0xffff;
  72        return stat | I2C_TIMEOUT;
  73}
  74
  75static void _flush_rx(struct i2c_regs *i2c_base)
  76{
  77        while (1) {
  78                if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
  79                        break;
  80
  81                REG(&(i2c_base->i2c_drr));
  82                REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
  83                udelay(1000);
  84        }
  85}
  86
  87static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
  88                                  uint speed)
  89{
  90        uint32_t        div, psc;
  91
  92        psc = 2;
  93        /* SCLL + SCLH */
  94        div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
  95        REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
  96        REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
  97        REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
  98
  99        return 0;
 100}
 101
 102static void _davinci_i2c_init(struct i2c_regs *i2c_base,
 103                              uint speed, int slaveadd)
 104{
 105        if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
 106                REG(&(i2c_base->i2c_con)) = 0;
 107                udelay(50000);
 108        }
 109
 110        _davinci_i2c_setspeed(i2c_base, speed);
 111
 112        REG(&(i2c_base->i2c_oa)) = slaveadd;
 113        REG(&(i2c_base->i2c_cnt)) = 0;
 114
 115        /* Interrupts must be enabled or I2C module won't work */
 116        REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
 117                I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
 118
 119        /* Now enable I2C controller (get it out of reset) */
 120        REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
 121
 122        udelay(1000);
 123}
 124
 125static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
 126                             uint32_t addr, int alen, uint8_t *buf, int len)
 127{
 128        uint32_t        tmp;
 129        int             i;
 130
 131        if ((alen < 0) || (alen > 2)) {
 132                printf("%s(): bogus address length %x\n", __func__, alen);
 133                return 1;
 134        }
 135
 136        if (_wait_for_bus(i2c_base))
 137                return 1;
 138
 139        if (alen != 0) {
 140                /* Start address phase */
 141                tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
 142                REG(&(i2c_base->i2c_cnt)) = alen;
 143                REG(&(i2c_base->i2c_sa)) = chip;
 144                REG(&(i2c_base->i2c_con)) = tmp;
 145
 146                tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 147
 148                CHECK_NACK();
 149
 150                switch (alen) {
 151                case 2:
 152                        /* Send address MSByte */
 153                        if (tmp & I2C_STAT_XRDY) {
 154                                REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
 155                        } else {
 156                                REG(&(i2c_base->i2c_con)) = 0;
 157                                return 1;
 158                        }
 159
 160                        tmp = _poll_i2c_irq(i2c_base,
 161                                            I2C_STAT_XRDY | I2C_STAT_NACK);
 162
 163                        CHECK_NACK();
 164                        /* No break, fall through */
 165                case 1:
 166                        /* Send address LSByte */
 167                        if (tmp & I2C_STAT_XRDY) {
 168                                REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
 169                        } else {
 170                                REG(&(i2c_base->i2c_con)) = 0;
 171                                return 1;
 172                        }
 173
 174                        tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
 175                                            I2C_STAT_NACK | I2C_STAT_ARDY);
 176
 177                        CHECK_NACK();
 178
 179                        if (!(tmp & I2C_STAT_ARDY)) {
 180                                REG(&(i2c_base->i2c_con)) = 0;
 181                                return 1;
 182                        }
 183                }
 184        }
 185
 186        /* Address phase is over, now read 'len' bytes and stop */
 187        tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
 188        REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
 189        REG(&(i2c_base->i2c_sa)) = chip;
 190        REG(&(i2c_base->i2c_con)) = tmp;
 191
 192        for (i = 0; i < len; i++) {
 193                tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
 194                                   I2C_STAT_ROVR);
 195
 196                CHECK_NACK();
 197
 198                if (tmp & I2C_STAT_RRDY) {
 199                        buf[i] = REG(&(i2c_base->i2c_drr));
 200                } else {
 201                        REG(&(i2c_base->i2c_con)) = 0;
 202                        return 1;
 203                }
 204        }
 205
 206        tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
 207
 208        CHECK_NACK();
 209
 210        if (!(tmp & I2C_STAT_SCD)) {
 211                REG(&(i2c_base->i2c_con)) = 0;
 212                return 1;
 213        }
 214
 215        _flush_rx(i2c_base);
 216        REG(&(i2c_base->i2c_stat)) = 0xffff;
 217        REG(&(i2c_base->i2c_cnt)) = 0;
 218        REG(&(i2c_base->i2c_con)) = 0;
 219
 220        return 0;
 221}
 222
 223static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
 224                              uint32_t addr, int alen, uint8_t *buf, int len)
 225{
 226        uint32_t        tmp;
 227        int             i;
 228
 229        if ((alen < 0) || (alen > 2)) {
 230                printf("%s(): bogus address length %x\n", __func__, alen);
 231                return 1;
 232        }
 233        if (len < 0) {
 234                printf("%s(): bogus length %x\n", __func__, len);
 235                return 1;
 236        }
 237
 238        if (_wait_for_bus(i2c_base))
 239                return 1;
 240
 241        /* Start address phase */
 242        tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
 243                I2C_CON_TRX | I2C_CON_STP;
 244        REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
 245                len & 0xffff : (len & 0xffff) + alen;
 246        REG(&(i2c_base->i2c_sa)) = chip;
 247        REG(&(i2c_base->i2c_con)) = tmp;
 248
 249        switch (alen) {
 250        case 2:
 251                /* Send address MSByte */
 252                tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 253
 254                CHECK_NACK();
 255
 256                if (tmp & I2C_STAT_XRDY) {
 257                        REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
 258                } else {
 259                        REG(&(i2c_base->i2c_con)) = 0;
 260                        return 1;
 261                }
 262                /* No break, fall through */
 263        case 1:
 264                /* Send address LSByte */
 265                tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 266
 267                CHECK_NACK();
 268
 269                if (tmp & I2C_STAT_XRDY) {
 270                        REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
 271                } else {
 272                        REG(&(i2c_base->i2c_con)) = 0;
 273                        return 1;
 274                }
 275        }
 276
 277        for (i = 0; i < len; i++) {
 278                tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 279
 280                CHECK_NACK();
 281
 282                if (tmp & I2C_STAT_XRDY)
 283                        REG(&(i2c_base->i2c_dxr)) = buf[i];
 284                else
 285                        return 1;
 286        }
 287
 288        tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
 289
 290        CHECK_NACK();
 291
 292        if (!(tmp & I2C_STAT_SCD)) {
 293                REG(&(i2c_base->i2c_con)) = 0;
 294                return 1;
 295        }
 296
 297        _flush_rx(i2c_base);
 298        REG(&(i2c_base->i2c_stat)) = 0xffff;
 299        REG(&(i2c_base->i2c_cnt)) = 0;
 300        REG(&(i2c_base->i2c_con)) = 0;
 301
 302        return 0;
 303}
 304
 305static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
 306{
 307        int     rc = 1;
 308
 309        if (chip == REG(&(i2c_base->i2c_oa)))
 310                return rc;
 311
 312        REG(&(i2c_base->i2c_con)) = 0;
 313        if (_wait_for_bus(i2c_base))
 314                return 1;
 315
 316        /* try to read one byte from current (or only) address */
 317        REG(&(i2c_base->i2c_cnt)) = 1;
 318        REG(&(i2c_base->i2c_sa))  = chip;
 319        REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
 320                                     I2C_CON_STP);
 321        udelay(50000);
 322
 323        if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
 324                rc = 0;
 325                _flush_rx(i2c_base);
 326                REG(&(i2c_base->i2c_stat)) = 0xffff;
 327        } else {
 328                REG(&(i2c_base->i2c_stat)) = 0xffff;
 329                REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
 330                udelay(20000);
 331                if (_wait_for_bus(i2c_base))
 332                        return 1;
 333        }
 334
 335        _flush_rx(i2c_base);
 336        REG(&(i2c_base->i2c_stat)) = 0xffff;
 337        REG(&(i2c_base->i2c_cnt)) = 0;
 338        return rc;
 339}
 340
 341#ifndef CONFIG_DM_I2C
 342static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
 343{
 344        switch (adap->hwadapnr) {
 345#if CONFIG_SYS_I2C_BUS_MAX >= 3
 346        case 2:
 347                return (struct i2c_regs *)I2C2_BASE;
 348#endif
 349#if CONFIG_SYS_I2C_BUS_MAX >= 2
 350        case 1:
 351                return (struct i2c_regs *)I2C1_BASE;
 352#endif
 353        case 0:
 354                return (struct i2c_regs *)I2C_BASE;
 355
 356        default:
 357                printf("wrong hwadapnr: %d\n", adap->hwadapnr);
 358        }
 359
 360        return NULL;
 361}
 362
 363static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 364{
 365        struct i2c_regs *i2c_base = davinci_get_base(adap);
 366        uint ret;
 367
 368        adap->speed = speed;
 369        ret =  _davinci_i2c_setspeed(i2c_base, speed);
 370
 371        return ret;
 372}
 373
 374static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
 375                             int slaveadd)
 376{
 377        struct i2c_regs *i2c_base = davinci_get_base(adap);
 378
 379        adap->speed = speed;
 380        _davinci_i2c_init(i2c_base, speed, slaveadd);
 381
 382        return;
 383}
 384
 385static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 386                            uint32_t addr, int alen, uint8_t *buf, int len)
 387{
 388        struct i2c_regs *i2c_base = davinci_get_base(adap);
 389        return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
 390}
 391
 392static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 393                             uint32_t addr, int alen, uint8_t *buf, int len)
 394{
 395        struct i2c_regs *i2c_base = davinci_get_base(adap);
 396
 397        return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
 398}
 399
 400static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
 401{
 402        struct i2c_regs *i2c_base = davinci_get_base(adap);
 403
 404        return _davinci_i2c_probe_chip(i2c_base, chip);
 405}
 406
 407U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
 408                         davinci_i2c_read, davinci_i2c_write,
 409                         davinci_i2c_setspeed,
 410                         CONFIG_SYS_DAVINCI_I2C_SPEED,
 411                         CONFIG_SYS_DAVINCI_I2C_SLAVE,
 412                         0)
 413
 414#if CONFIG_SYS_I2C_BUS_MAX >= 2
 415U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
 416                         davinci_i2c_read, davinci_i2c_write,
 417                         davinci_i2c_setspeed,
 418                         CONFIG_SYS_DAVINCI_I2C_SPEED1,
 419                         CONFIG_SYS_DAVINCI_I2C_SLAVE1,
 420                         1)
 421#endif
 422
 423#if CONFIG_SYS_I2C_BUS_MAX >= 3
 424U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
 425                         davinci_i2c_read, davinci_i2c_write,
 426                         davinci_i2c_setspeed,
 427                         CONFIG_SYS_DAVINCI_I2C_SPEED2,
 428                         CONFIG_SYS_DAVINCI_I2C_SLAVE2,
 429                         2)
 430#endif
 431
 432#else /* CONFIG_DM_I2C */
 433
 434static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 435                          int nmsgs)
 436{
 437        struct i2c_bus *i2c_bus = dev_get_priv(bus);
 438        int ret;
 439
 440        debug("i2c_xfer: %d messages\n", nmsgs);
 441        for (; nmsgs > 0; nmsgs--, msg++) {
 442                debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 443                if (msg->flags & I2C_M_RD) {
 444                        ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
 445                                0, 0, msg->buf, msg->len);
 446                } else {
 447                        ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
 448                                0, 0, msg->buf, msg->len);
 449                }
 450                if (ret) {
 451                        debug("i2c_write: error sending\n");
 452                        return -EREMOTEIO;
 453                }
 454        }
 455
 456        return ret;
 457}
 458
 459static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
 460{
 461        struct i2c_bus *i2c_bus = dev_get_priv(dev);
 462
 463        i2c_bus->speed = speed;
 464        return _davinci_i2c_setspeed(i2c_bus->regs, speed);
 465}
 466
 467static int davinci_i2c_probe(struct udevice *dev)
 468{
 469        struct i2c_bus *i2c_bus = dev_get_priv(dev);
 470
 471        i2c_bus->id = dev->seq;
 472        i2c_bus->regs = (struct i2c_regs *)devfdt_get_addr(dev);
 473
 474        i2c_bus->speed = 100000;
 475         _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
 476
 477        return 0;
 478}
 479
 480static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 481                                  uint chip_flags)
 482{
 483        struct i2c_bus *i2c_bus = dev_get_priv(bus);
 484
 485        return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
 486}
 487
 488static const struct dm_i2c_ops davinci_i2c_ops = {
 489        .xfer           = davinci_i2c_xfer,
 490        .probe_chip     = davinci_i2c_probe_chip,
 491        .set_bus_speed  = davinci_i2c_set_speed,
 492};
 493
 494static const struct udevice_id davinci_i2c_ids[] = {
 495        { .compatible = "ti,davinci-i2c"},
 496        { .compatible = "ti,keystone-i2c"},
 497        { }
 498};
 499
 500U_BOOT_DRIVER(i2c_davinci) = {
 501        .name   = "i2c_davinci",
 502        .id     = UCLASS_I2C,
 503        .of_match = davinci_i2c_ids,
 504        .probe  = davinci_i2c_probe,
 505        .priv_auto_alloc_size = sizeof(struct i2c_bus),
 506        .ops    = &davinci_i2c_ops,
 507};
 508
 509#endif /* CONFIG_DM_I2C */
 510