LXR uboot/drivers/mtd/nand/kb9202

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2006
   4 * KwikByte <kb9200_dev@kwikbyte.com>
   5 *
   6 * (C) Copyright 2009
   7 * Matthias Kaehlcke <matthias@kaehlcke.net>
   8 */
   9
  10#include <common.h>
  11#include <asm/io.h>
  12#include <asm/arch/AT91RM9200.h>
  13#include <asm/arch/hardware.h>
  14
  15#include <nand.h>
  16
  17/*
  18 *      hardware specific access to control-lines
  19 */
  20
  21#define MASK_ALE        (1 << 22)       /* our ALE is A22 */
  22#define MASK_CLE        (1 << 21)       /* our CLE is A21 */
  23
  24#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
  25#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
  26
  27#define KB9202_SMC2_NWS (1 << 2)
  28#define KB9202_SMC2_TDF (1 << 8)
  29#define KB9202_SMC2_RWSETUP (1 << 24)
  30#define KB9202_SMC2_RWHOLD (1 << 29)
  31
  32/*
  33 *      Board-specific function to access device control signals
  34 */
  35static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  36{
  37        struct nand_chip *this = mtd_to_nand(mtd);
  38
  39        if (ctrl & NAND_CTRL_CHANGE) {
  40                ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  41
  42                /* clear ALE and CLE bits */
  43                IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
  44
  45                if (ctrl & NAND_CLE)
  46                        IO_ADDR_W |= MASK_CLE;
  47
  48                if (ctrl & NAND_ALE)
  49                        IO_ADDR_W |= MASK_ALE;
  50
  51                this->IO_ADDR_W = (void *) IO_ADDR_W;
  52
  53                if (ctrl & NAND_NCE)
  54                        writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
  55                else
  56                        writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  57        }
  58
  59        if (cmd != NAND_CMD_NONE)
  60                writeb(cmd, this->IO_ADDR_W);
  61}
  62
  63
  64/*
  65 * Board-specific function to access the device ready signal.
  66 */
  67static int kb9202_nand_ready(struct mtd_info *mtd)
  68{
  69        return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
  70}
  71
  72
  73/*
  74 * Board-specific NAND init.  Copied from include/linux/mtd/nand.h for reference.
  75 *
  76 * struct nand_chip - NAND Private Flash Chip Data
  77 * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  78 * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  79 * @hwcontrol:          [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
  80 * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  81 *                      If set to NULL no access to ready/busy is available and the ready/busy information
  82 *                      is read from the chip status register
  83 * @enable_hwecc:       [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
  84 *                      be provided if a hardware ECC is available
  85 * @eccmode:            [BOARDSPECIFIC] mode of ecc, see defines
  86 * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
  87 * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
  88 *                      special functionality. See the defines for further explanation
  89*/
  90/*
  91 * This routine initializes controller and GPIOs.
  92 */
  93int board_nand_init(struct nand_chip *nand)
  94{
  95        unsigned int value;
  96
  97        nand->ecc.mode = NAND_ECC_SOFT;
  98        nand->cmd_ctrl = kb9202_nand_hwcontrol;
  99        nand->dev_ready = kb9202_nand_ready;
 100
 101        /* in case running outside of bootloader */
 102        writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
 103
 104        /* setup nand flash access (allow ample margin) */
 105        /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
 106        writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
 107                AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
 108                AT91C_SMC_CSR3);
 109
 110        /* enable internal NAND controller */
 111        value = readl(AT91C_EBI_CSA);
 112        value |= AT91C_EBI_CS3A_SMC_SmartMedia;
 113        writel(value, AT91C_EBI_CSA);
 114
 115        /* enable SMOE/SMWE */
 116        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
 117        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
 118        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
 119
 120        /* set NCE to high */
 121        writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
 122
 123        /* disable output on pin connected to the busy line of the NAND */
 124        writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
 125
 126        /* enable the PIO to control NCE and BUSY */
 127        writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
 128
 129        /* enable output for NCE */
 130        writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
 131
 132        return (0);
 133}
 134