1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF53017EVB. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M53017EVB_H 14#define _M53017EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_WATCHDOG 25#define CONFIG_WATCHDOG_TIMEOUT 5000 26 27#define CONFIG_SYS_UNIFY_CACHE 28 29#define CONFIG_MCFFEC 30#ifdef CONFIG_MCFFEC 31# define CONFIG_MII 1 32# define CONFIG_MII_INIT 1 33# define CONFIG_SYS_DISCOVER_PHY 34# define CONFIG_SYS_RX_ETH_BUFFER 8 35# define CONFIG_SYS_TX_ETH_BUFFER 8 36# define CONFIG_SYS_FEC_BUF_USE_SRAM 37# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 38# define CONFIG_HAS_ETH1 39 40# define CONFIG_SYS_FEC0_PINMUX 0 41# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 42# define CONFIG_SYS_FEC1_PINMUX 0 43# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 44# define MCFFEC_TOUT_LOOP 50000 45 46/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 47# ifndef CONFIG_SYS_DISCOVER_PHY 48# define FECDUPLEX FULL 49# define FECSPEED _100BASET 50# else 51# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53# endif 54# endif /* CONFIG_SYS_DISCOVER_PHY */ 55#endif 56 57#define CONFIG_MCFRTC 58#undef RTC_DEBUG 59#define CONFIG_SYS_RTC_CNT (0x8000) 60#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 61 62/* Timer */ 63#define CONFIG_MCFTMR 64#undef CONFIG_MCFPIT 65 66/* I2C */ 67#define CONFIG_SYS_I2C 68#define CONFIG_SYS_I2C_FSL 69#define CONFIG_SYS_FSL_I2C_SPEED 80000 70#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 71#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 72#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 73 74#define CONFIG_UDP_CHECKSUM 75 76#ifdef CONFIG_MCFFEC 77# define CONFIG_IPADDR 192.162.1.2 78# define CONFIG_NETMASK 255.255.255.0 79# define CONFIG_SERVERIP 192.162.1.1 80# define CONFIG_GATEWAYIP 192.162.1.1 81#endif /* FEC_ENET */ 82 83#define CONFIG_HOSTNAME "M53017" 84#define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "loadaddr=40010000\0" \ 87 "u-boot=u-boot.bin\0" \ 88 "load=tftp ${loadaddr) ${u-boot}\0" \ 89 "upd=run load; run prog\0" \ 90 "prog=prot off 0 3ffff;" \ 91 "era 0 3ffff;" \ 92 "cp.b ${loadaddr} 0 ${filesize};" \ 93 "save\0" \ 94 "" 95 96#define CONFIG_PRAM 512 /* 512 KB */ 97 98#define CONFIG_SYS_LOAD_ADDR 0x40010000 99 100#define CONFIG_SYS_CLK 80000000 101#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 102 103#define CONFIG_SYS_MBAR 0xFC000000 104 105/* 106 * Low Level Configuration Settings 107 * (address mappings, register initial values, etc.) 108 * You should know what you are doing if you make changes here. 109 */ 110/* 111 * Definitions for initial stack pointer and data area (in DPRAM) 112 */ 113#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 114#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 115#define CONFIG_SYS_INIT_RAM_CTRL 0x221 116#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 117#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 118 119/* 120 * Start addresses for the final memory configuration 121 * (Set up by the startup code) 122 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 123 */ 124#define CONFIG_SYS_SDRAM_BASE 0x40000000 125#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 126#define CONFIG_SYS_SDRAM_CFG1 0x43711630 127#define CONFIG_SYS_SDRAM_CFG2 0x56670000 128#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 129#define CONFIG_SYS_SDRAM_EMOD 0x80010000 130#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 131 132#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 133#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 134 135#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 136#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 137 138#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 139#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 140 141/* 142 * For booting Linux, the board info and command line data 143 * have to be in the first 8 MB of memory, since this is 144 * the maximum mapped by the Linux kernel during initialization ?? 145 */ 146#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 147#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 148 149/*----------------------------------------------------------------------- 150 * FLASH organization 151 */ 152#define CONFIG_SYS_FLASH_CFI 153#ifdef CONFIG_SYS_FLASH_CFI 154# define CONFIG_FLASH_CFI_DRIVER 1 155# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 156# define CONFIG_FLASH_SPANSION_S29WS_N 1 157# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 158# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 159# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 160# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 161# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 162#endif 163 164#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 165 166/* Configuration for environment 167 * Environment is embedded in u-boot in the second sector of the flash 168 */ 169#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 170#define CONFIG_ENV_SIZE 0x1000 171#define CONFIG_ENV_SECT_SIZE 0x8000 172 173#define LDS_BOARD_TEXT \ 174 . = DEFINED(env_offset) ? env_offset : .; \ 175 env/embedded.o(.text*) 176 177/*----------------------------------------------------------------------- 178 * Cache Configuration 179 */ 180#define CONFIG_SYS_CACHELINE_SIZE 16 181 182#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 8) 184#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 4) 186#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 187#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 188 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 189 CF_ACR_EN | CF_ACR_SM_ALL) 190#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 191 CF_CACR_DCM_P) 192 193/*----------------------------------------------------------------------- 194 * Chipselect bank definitions 195 */ 196/* 197 * CS0 - NOR Flash 198 * CS1 - Ext SRAM 199 * CS2 - Available 200 * CS3 - Available 201 * CS4 - Available 202 * CS5 - Available 203 */ 204#define CONFIG_SYS_CS0_BASE 0 205#define CONFIG_SYS_CS0_MASK 0x00FF0001 206#define CONFIG_SYS_CS0_CTRL 0x00001FA0 207 208#define CONFIG_SYS_CS1_BASE 0xC0000000 209#define CONFIG_SYS_CS1_MASK 0x00070001 210#define CONFIG_SYS_CS1_CTRL 0x00001FA0 211 212#endif /* _M53017EVB_H */ 213