1
2
3
4
5
6
7
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#define CONFIG_FSL_SATA_V2
13#define CONFIG_PCIE4
14
15#define CONFIG_ICS307_REFCLK_HZ 25000000
16
17#ifdef CONFIG_RAMBOOT_PBL
18#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
19#ifndef CONFIG_SDCARD
20#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22#else
23#define CONFIG_SPL_FLUSH_IMAGE
24#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
25#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
26#define CONFIG_SPL_PAD_TO 0x40000
27#define CONFIG_SPL_MAX_SIZE 0x28000
28#define RESET_VECTOR_OFFSET 0x27FFC
29#define BOOT_PAGE_OFFSET 0x27000
30
31#ifdef CONFIG_SDCARD
32#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
33#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
34#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
35#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
36#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
37#ifndef CONFIG_SPL_BUILD
38#define CONFIG_SYS_MPC85XX_NO_RESETVEC
39#endif
40#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
41#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
42#define CONFIG_SPL_MMC_BOOT
43#endif
44
45#ifdef CONFIG_SPL_BUILD
46#define CONFIG_SPL_SKIP_RELOCATE
47#define CONFIG_SPL_COMMON_INIT_DDR
48#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
49#endif
50
51#endif
52#endif
53
54#define CONFIG_DDR_ECC
55
56
57#define CONFIG_SYS_BOOK3E_HV
58#define CONFIG_MP
59
60#ifndef CONFIG_RESET_VECTOR_ADDRESS
61#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62#endif
63
64#define CONFIG_SYS_FSL_CPC
65#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
66#define CONFIG_PCIE1
67#define CONFIG_PCIE2
68#define CONFIG_PCIE3
69#define CONFIG_FSL_PCI_INIT
70#define CONFIG_SYS_PCI_64BIT
71
72#define CONFIG_ENV_OVERWRITE
73
74
75
76
77#define CONFIG_SYS_CACHE_STASHING
78#define CONFIG_BTB
79#ifdef CONFIG_DDR_ECC
80#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
81#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
82#endif
83
84#define CONFIG_ENABLE_36BIT_PHYS
85
86#define CONFIG_ADDR_MAP
87#define CONFIG_SYS_NUM_ADDR_MAP 64
88
89#define CONFIG_SYS_MEMTEST_START 0x00200000
90#define CONFIG_SYS_MEMTEST_END 0x00400000
91
92
93
94
95#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
96#define CONFIG_SYS_L3_SIZE (512 << 10)
97#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
98#ifdef CONFIG_RAMBOOT_PBL
99#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
100#endif
101#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
102#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
103#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
104#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
105
106#define CONFIG_SYS_DCSRBAR 0xf0000000
107#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
108
109
110
111
112#define CONFIG_VERY_BIG_RAM
113#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
114#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
115
116#define CONFIG_DIMM_SLOTS_PER_CTLR 1
117#define CONFIG_CHIP_SELECTS_PER_CTRL 4
118#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
119
120#define CONFIG_DDR_SPD
121
122
123
124
125#define CONFIG_SYS_FLASH_BASE 0xe0000000
126#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
127
128#ifdef CONFIG_SPL_BUILD
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
130#else
131#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
132#endif
133
134#define CONFIG_MISC_INIT_R
135
136#define CONFIG_HWCONFIG
137
138
139#define CONFIG_L1_INIT_RAM
140#define CONFIG_SYS_INIT_RAM_LOCK
141#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
142#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
143#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
144
145#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
146 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
147 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
148#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
149
150#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
151 GENERATED_GBL_DATA_SIZE)
152#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
153
154#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
155#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
156
157
158
159
160
161#define CONFIG_SYS_NS16550_SERIAL
162#define CONFIG_SYS_NS16550_REG_SIZE 1
163#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
164
165#define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
167
168#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
169#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
170#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
171#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
172
173
174#define CONFIG_SYS_I2C
175#define CONFIG_SYS_I2C_FSL
176#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
177#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
178#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
179#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
180
181
182
183
184
185
186
187#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
188#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
189#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
190#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
191#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
192#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
193#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
194#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
195
196
197#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
198#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
199#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
200#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
201#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
202#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
203#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
204#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
205
206
207#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
208#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
209#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
210#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
211#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
212#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
213#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
214#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
215
216
217#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
218#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
219#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000
220#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
221#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
222#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
223
224#ifdef CONFIG_PCI
225#define CONFIG_PCI_INDIRECT_BRIDGE
226
227#define CONFIG_PCI_SCAN_SHOW
228#endif
229
230
231#ifdef CONFIG_FSL_SATA_V2
232#define CONFIG_SYS_SATA_MAX_DEVICE 2
233#define CONFIG_SATA1
234#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
235#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
236#define CONFIG_SATA2
237#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
238#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
239
240#define CONFIG_LBA48
241#endif
242
243#ifdef CONFIG_FMAN_ENET
244#define CONFIG_MII
245#define CONFIG_ETHPRIME "FM1@DTSEC1"
246#endif
247
248
249
250
251#define CONFIG_LOADS_ECHO
252#define CONFIG_SYS_LOADS_BAUD_CHANGE
253
254
255
256
257
258
259
260
261#define CONFIG_SYS_LOAD_ADDR 0x2000000
262
263
264
265
266
267
268#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
269#define CONFIG_SYS_BOOTM_LEN (64 << 20)
270
271#ifdef CONFIG_CMD_KGDB
272#define CONFIG_KGDB_BAUDRATE 230400
273#endif
274
275
276
277
278#define CONFIG_ROOTPATH "/opt/nfsroot"
279#define CONFIG_BOOTFILE "uImage"
280#define CONFIG_UBOOTPATH "u-boot.bin"
281
282
283#define CONFIG_LOADADDR 1000000
284
285#define CONFIG_HVBOOT \
286 "setenv bootargs config-addr=0x60000000; " \
287 "bootm 0x01000000 - 0x00f00000"
288
289#ifndef CONFIG_MTD_NOR_FLASH
290#else
291#define CONFIG_FLASH_CFI_DRIVER
292#define CONFIG_SYS_FLASH_CFI
293#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
294#endif
295
296#if defined(CONFIG_SPIFLASH)
297#define CONFIG_SYS_EXTRA_ENV_RELOC
298#define CONFIG_ENV_SPI_BUS 0
299#define CONFIG_ENV_SPI_CS 0
300#define CONFIG_ENV_SPI_MAX_HZ 10000000
301#define CONFIG_ENV_SPI_MODE 0
302#define CONFIG_ENV_SIZE 0x2000
303#define CONFIG_ENV_OFFSET 0x100000
304#define CONFIG_ENV_SECT_SIZE 0x10000
305#elif defined(CONFIG_SDCARD)
306#define CONFIG_SYS_EXTRA_ENV_RELOC
307#define CONFIG_SYS_MMC_ENV_DEV 0
308#define CONFIG_ENV_SIZE 0x2000
309#define CONFIG_ENV_OFFSET (512 * 0x800)
310#elif defined(CONFIG_NAND)
311#define CONFIG_SYS_EXTRA_ENV_RELOC
312#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
313#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
314#elif defined(CONFIG_ENV_IS_NOWHERE)
315#define CONFIG_ENV_SIZE 0x2000
316#else
317#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
318#define CONFIG_ENV_SIZE 0x2000
319#define CONFIG_ENV_SECT_SIZE 0x20000
320#endif
321
322#define CONFIG_SYS_CLK_FREQ 66666666
323#define CONFIG_DDR_CLK_FREQ 133333333
324
325#ifndef __ASSEMBLY__
326unsigned long get_board_sys_clk(void);
327unsigned long get_board_ddr_clk(void);
328#endif
329
330
331
332
333#define CONFIG_SYS_SPD_BUS_NUM 0
334#define SPD_EEPROM_ADDRESS1 0x52
335#define SPD_EEPROM_ADDRESS2 0x54
336#define SPD_EEPROM_ADDRESS3 0x56
337#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
338#define CONFIG_SYS_SDRAM_SIZE 4096
339
340
341
342
343#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
344#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
345 + 0x8000000) | \
346 CSPR_PORT_SIZE_16 | \
347 CSPR_MSEL_NOR | \
348 CSPR_V)
349#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
350#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
351 CSPR_PORT_SIZE_16 | \
352 CSPR_MSEL_NOR | \
353 CSPR_V)
354#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
355
356#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
357
358#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
359 FTIM0_NOR_TEADC(0x5) | \
360 FTIM0_NOR_TEAHC(0x5))
361#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
362 FTIM1_NOR_TRAD_NOR(0x1A) |\
363 FTIM1_NOR_TSEQRAD_NOR(0x13))
364#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
365 FTIM2_NOR_TCH(0x4) | \
366 FTIM2_NOR_TWPH(0x0E) | \
367 FTIM2_NOR_TWP(0x1c))
368#define CONFIG_SYS_NOR_FTIM3 0x0
369
370#define CONFIG_SYS_FLASH_QUIET_TEST
371#define CONFIG_FLASH_SHOW_PROGRESS 45
372
373#define CONFIG_SYS_MAX_FLASH_BANKS 2
374#define CONFIG_SYS_MAX_FLASH_SECT 1024
375#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
376#define CONFIG_SYS_FLASH_WRITE_TOUT 500
377
378#define CONFIG_SYS_FLASH_EMPTY_INFO
379#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
380 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
381
382
383#define CONFIG_NAND_FSL_IFC
384#define CONFIG_SYS_NAND_MAX_ECCPOS 256
385#define CONFIG_SYS_NAND_MAX_OOBFREE 2
386#define CONFIG_SYS_NAND_BASE 0xff800000
387#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
388
389#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
390#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
391 | CSPR_PORT_SIZE_8 \
392 | CSPR_MSEL_NAND \
393 | CSPR_V)
394#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
395
396#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
397 | CSOR_NAND_ECC_DEC_EN \
398 | CSOR_NAND_ECC_MODE_4 \
399 | CSOR_NAND_RAL_3 \
400 | CSOR_NAND_PGS_4K \
401 | CSOR_NAND_SPRZ_224 \
402 | CSOR_NAND_PB(128))
403
404#define CONFIG_SYS_NAND_ONFI_DETECTION
405
406
407#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
408 FTIM0_NAND_TWP(0x18) | \
409 FTIM0_NAND_TWCHT(0x07) | \
410 FTIM0_NAND_TWH(0x0a))
411#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
412 FTIM1_NAND_TWBE(0x39) | \
413 FTIM1_NAND_TRR(0x0e) | \
414 FTIM1_NAND_TRP(0x18))
415#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
416 FTIM2_NAND_TREH(0x0a) | \
417 FTIM2_NAND_TWHRE(0x1e))
418#define CONFIG_SYS_NAND_FTIM3 0x0
419
420#define CONFIG_SYS_NAND_DDR_LAW 11
421#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
422#define CONFIG_SYS_MAX_NAND_DEVICE 1
423
424#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
425
426#if defined(CONFIG_NAND)
427#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
428#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
429#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
430#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
431#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
432#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
433#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
434#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
435#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
436#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
437#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
438#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
439#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
440#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
441#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
442#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
443#else
444#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
445#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
446#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
447#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
448#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
449#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
450#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
451#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
452#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
453#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
454#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
455#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
456#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
457#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
458#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
459#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
460#endif
461#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
462#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
463#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
464#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
465#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
466#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
467#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
468#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
469
470
471#define CONFIG_SYS_CPLD_BASE 0xffdf0000
472#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
473#define CONFIG_SYS_CSPR3_EXT (0xf)
474#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
475 | CSPR_PORT_SIZE_8 \
476 | CSPR_MSEL_GPCM \
477 | CSPR_V)
478
479#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
480#define CONFIG_SYS_CSOR3 0x0
481
482
483#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
484 FTIM0_GPCM_TEADC(0x0e) | \
485 FTIM0_GPCM_TEAHC(0x0e))
486#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
487 FTIM1_GPCM_TRAD(0x1f))
488#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
489 FTIM2_GPCM_TCH(0x8) | \
490 FTIM2_GPCM_TWP(0x1f))
491#define CONFIG_SYS_CS3_FTIM3 0x0
492
493#if defined(CONFIG_RAMBOOT_PBL)
494#define CONFIG_SYS_RAMBOOT
495#endif
496
497
498#define CONFIG_SYS_FSL_I2C_SPEED 100000
499#define CONFIG_SYS_FSL_I2C2_SPEED 100000
500#define I2C_MUX_PCA_ADDR_PRI 0x77
501#define I2C_MUX_PCA_ADDR_SEC 0x76
502
503#define I2C_MUX_CH_DEFAULT 0x8
504#define I2C_MUX_CH_VOL_MONITOR 0xa
505#define I2C_MUX_CH_VSC3316_FS 0xc
506#define I2C_MUX_CH_VSC3316_BS 0xd
507
508
509#define I2C_VOL_MONITOR_ADDR 0x40
510#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
511#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
512#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
513
514#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
515#ifndef CONFIG_SPL_BUILD
516#define CONFIG_VID
517#endif
518#define CONFIG_VOL_MONITOR_IR36021_SET
519#define CONFIG_VOL_MONITOR_IR36021_READ
520
521#define VDD_MV_MIN 819
522#define VDD_MV_MAX 1212
523
524
525
526
527#define CONFIG_SF_DEFAULT_SPEED 10000000
528#define CONFIG_SF_DEFAULT_MODE 0
529
530
531#ifndef CONFIG_NOBQFMAN
532#define CONFIG_SYS_BMAN_NUM_PORTALS 50
533#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
534#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
535#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
536#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
537#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
538#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
539#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
540#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
541 CONFIG_SYS_BMAN_CENA_SIZE)
542#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
543#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
544#define CONFIG_SYS_QMAN_NUM_PORTALS 50
545#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
546#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
547#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
548#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
549#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
550#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
551#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
552#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
553 CONFIG_SYS_QMAN_CENA_SIZE)
554#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
555#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
556
557#define CONFIG_SYS_DPAA_FMAN
558#define CONFIG_SYS_DPAA_PME
559#define CONFIG_SYS_PMAN
560#define CONFIG_SYS_DPAA_DCE
561#define CONFIG_SYS_DPAA_RMAN
562#define CONFIG_SYS_INTERLAKEN
563
564
565#if defined(CONFIG_SPIFLASH)
566
567
568
569
570#define CONFIG_SYS_QE_FW_IN_SPIFLASH
571#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
572#elif defined(CONFIG_SDCARD)
573
574
575
576
577
578#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
579#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
580#elif defined(CONFIG_NAND)
581#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
582#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
583#else
584#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
585#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
586#endif
587#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
588#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
589#endif
590
591#ifdef CONFIG_SYS_DPAA_FMAN
592#define CONFIG_FMAN_ENET
593#define CONFIG_PHYLIB_10G
594#define CONFIG_PHY_VITESSE
595#define CONFIG_PHY_CORTINA
596#define CONFIG_SYS_CORTINA_FW_IN_NOR
597#define CONFIG_CORTINA_FW_ADDR 0xefe00000
598#define CONFIG_CORTINA_FW_LENGTH 0x40000
599#define CONFIG_PHY_TERANETICS
600#define SGMII_PHY_ADDR1 0x0
601#define SGMII_PHY_ADDR2 0x1
602#define SGMII_PHY_ADDR3 0x2
603#define SGMII_PHY_ADDR4 0x3
604#define SGMII_PHY_ADDR5 0x4
605#define SGMII_PHY_ADDR6 0x5
606#define SGMII_PHY_ADDR7 0x6
607#define SGMII_PHY_ADDR8 0x7
608#define FM1_10GEC1_PHY_ADDR 0x10
609#define FM1_10GEC2_PHY_ADDR 0x11
610#define FM2_10GEC1_PHY_ADDR 0x12
611#define FM2_10GEC2_PHY_ADDR 0x13
612#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
613#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
614#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
615#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
616#endif
617
618
619#ifdef CONFIG_FSL_SATA_V2
620#define CONFIG_SYS_SATA_MAX_DEVICE 2
621#define CONFIG_SATA1
622#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
623#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
624#define CONFIG_SATA2
625#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
626#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
627
628#define CONFIG_LBA48
629#endif
630
631#ifdef CONFIG_FMAN_ENET
632#define CONFIG_MII
633#define CONFIG_ETHPRIME "FM1@DTSEC1"
634#endif
635
636
637
638
639#define CONFIG_USB_EHCI_FSL
640#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
641#define CONFIG_HAS_FSL_DR_USB
642
643#ifdef CONFIG_MMC
644#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
645#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
646#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
647#endif
648
649
650#define __USB_PHY_TYPE utmi
651
652
653
654
655
656
657
658#ifdef CONFIG_ARCH_T4240
659#define CTRL_INTLV_PREFERED 3way_4KB
660#else
661#define CTRL_INTLV_PREFERED cacheline
662#endif
663
664#define CONFIG_EXTRA_ENV_SETTINGS \
665 "hwconfig=fsl_ddr:" \
666 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
667 "bank_intlv=auto;" \
668 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
669 "netdev=eth0\0" \
670 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
671 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
672 "tftpflash=tftpboot $loadaddr $uboot && " \
673 "protect off $ubootaddr +$filesize && " \
674 "erase $ubootaddr +$filesize && " \
675 "cp.b $loadaddr $ubootaddr $filesize && " \
676 "protect on $ubootaddr +$filesize && " \
677 "cmp.b $loadaddr $ubootaddr $filesize\0" \
678 "consoledev=ttyS0\0" \
679 "ramdiskaddr=2000000\0" \
680 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
681 "fdtaddr=1e00000\0" \
682 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
683 "bdev=sda3\0"
684
685#define CONFIG_HVBOOT \
686 "setenv bootargs config-addr=0x60000000; " \
687 "bootm 0x01000000 - 0x00f00000"
688
689#define CONFIG_LINUX \
690 "setenv bootargs root=/dev/ram rw " \
691 "console=$consoledev,$baudrate $othbootargs;" \
692 "setenv ramdiskaddr 0x02000000;" \
693 "setenv fdtaddr 0x00c00000;" \
694 "setenv loadaddr 0x1000000;" \
695 "bootm $loadaddr $ramdiskaddr $fdtaddr"
696
697#define CONFIG_HDBOOT \
698 "setenv bootargs root=/dev/$bdev rw " \
699 "console=$consoledev,$baudrate $othbootargs;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr - $fdtaddr"
703
704#define CONFIG_NFSBOOTCOMMAND \
705 "setenv bootargs root=/dev/nfs rw " \
706 "nfsroot=$serverip:$rootpath " \
707 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
708 "console=$consoledev,$baudrate $othbootargs;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr - $fdtaddr"
712
713#define CONFIG_RAMBOOTCOMMAND \
714 "setenv bootargs root=/dev/ram rw " \
715 "console=$consoledev,$baudrate $othbootargs;" \
716 "tftp $ramdiskaddr $ramdiskfile;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr $ramdiskaddr $fdtaddr"
720
721#define CONFIG_BOOTCOMMAND CONFIG_LINUX
722
723#include <asm/fsl_secure_boot.h>
724
725#endif
726