1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7/* 8 * TQM8349 board configuration file 9 */ 10 11#ifndef __CONFIG_H 12#define __CONFIG_H 13 14/* 15 * High Level Configuration Options 16 */ 17#define CONFIG_E300 1 /* E300 Family */ 18#define CONFIG_MPC834x 1 /* MPC834x specific */ 19#define CONFIG_MPC8349 1 /* MPC8349 specific */ 20 21/* IMMR Base Address Register, use Freescale default: 0xff400000 */ 22#define CONFIG_SYS_IMMR 0xff400000 23 24/* System clock. Primary input clock when in PCI host mode */ 25#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 26 27/* 28 * Local Bus LCRR 29 * LCRR: DLL bypass, Clock divider is 8 30 * 31 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 32 * 33 * External Local Bus rate is 34 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 35 */ 36#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 37#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 38 39/* board pre init: do not call, nothing to do */ 40 41/* detect the number of flash banks */ 42 43/* 44 * DDR Setup 45 */ 46 /* DDR is system memory*/ 47#define CONFIG_SYS_DDR_BASE 0x00000000 48#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 49#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 50#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 51#undef CONFIG_DDR_ECC /* only for ECC DDR module */ 52#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 53 54#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 55#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 56#define CONFIG_SYS_MEMTEST_END 0x00100000 57 58/* 59 * FLASH on the Local Bus 60 */ 61#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 62#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 63#undef CONFIG_SYS_FLASH_CHECKSUM 64#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 65#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 66#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 67#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 68 69/* 70 * FLASH bank number detection 71 */ 72 73/* 74 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 75 * Flash banks has to be determined at runtime and stored in a gloabl variable 76 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 77 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 78 * flash_info, and should be made sufficiently large to accomodate the number 79 * of banks that might actually be detected. Since most (all?) Flash related 80 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 81 * the board, it is defined as tqm834x_num_flash_banks. 82 */ 83#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 84 85#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 86 87/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 88#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 89 | BR_MS_GPCM \ 90 | BR_PS_32 \ 91 | BR_V) 92 93/* FLASH timing (0x0000_0c54) */ 94#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 95 | OR_GPCM_ACS_DIV4 \ 96 | OR_GPCM_SCY_5 \ 97 | OR_GPCM_TRLX) 98 99#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 100 101#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 102 | CONFIG_SYS_OR_TIMING_FLASH) 103 104#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 105 106 /* Window base at flash base */ 107#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 108 109/* disable remaining mappings */ 110#define CONFIG_SYS_BR1_PRELIM 0x00000000 111#define CONFIG_SYS_OR1_PRELIM 0x00000000 112#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 113#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 114 115#define CONFIG_SYS_BR2_PRELIM 0x00000000 116#define CONFIG_SYS_OR2_PRELIM 0x00000000 117#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 118#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 119 120#define CONFIG_SYS_BR3_PRELIM 0x00000000 121#define CONFIG_SYS_OR3_PRELIM 0x00000000 122#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 123#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 124 125/* 126 * Monitor config 127 */ 128#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 129 130#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 131# define CONFIG_SYS_RAMBOOT 132#else 133# undef CONFIG_SYS_RAMBOOT 134#endif 135 136#define CONFIG_SYS_INIT_RAM_LOCK 1 137#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 138#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 139 140#define CONFIG_SYS_GBL_DATA_OFFSET \ 141 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 142#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 143 144 /* Reserve 384 kB = 3 sect. for Mon */ 145#define CONFIG_SYS_MONITOR_LEN (384 * 1024) 146 /* Reserve 512 kB for malloc */ 147#define CONFIG_SYS_MALLOC_LEN (512 * 1024) 148 149/* 150 * Serial Port 151 */ 152#define CONFIG_SYS_NS16550_SERIAL 153#define CONFIG_SYS_NS16550_REG_SIZE 1 154#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 155 156#define CONFIG_SYS_BAUDRATE_TABLE \ 157 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 158 159#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 160#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 161 162/* 163 * I2C 164 */ 165#define CONFIG_SYS_I2C 166#define CONFIG_SYS_I2C_FSL 167#define CONFIG_SYS_FSL_I2C_SPEED 400000 168#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 169#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 170 171/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 172#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 173#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 174#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 175#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 176 177/* I2C RTC */ 178#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 179#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 180 181/* 182 * TSEC 183 */ 184#define CONFIG_MII 185 186#define CONFIG_SYS_TSEC1_OFFSET 0x24000 187#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 188#define CONFIG_SYS_TSEC2_OFFSET 0x25000 189#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 190 191#if defined(CONFIG_TSEC_ENET) 192 193#define CONFIG_TSEC1 1 194#define CONFIG_TSEC1_NAME "TSEC0" 195#define CONFIG_TSEC2 1 196#define CONFIG_TSEC2_NAME "TSEC1" 197#define TSEC1_PHY_ADDR 2 198#define TSEC2_PHY_ADDR 1 199#define TSEC1_PHYIDX 0 200#define TSEC2_PHYIDX 0 201#define TSEC1_FLAGS TSEC_GIGABIT 202#define TSEC2_FLAGS TSEC_GIGABIT 203 204/* Options are: TSEC[0-1] */ 205#define CONFIG_ETHPRIME "TSEC0" 206 207#endif /* CONFIG_TSEC_ENET */ 208 209#if defined(CONFIG_PCI) 210 211#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 212 213/* PCI1 host bridge */ 214#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 215#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 216#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 217#define CONFIG_SYS_PCI1_MMIO_BASE \ 218 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 219#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 220#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 221#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 222#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 223#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 224 225#undef CONFIG_EEPRO100 226#define CONFIG_EEPRO100 227#undef CONFIG_TULIP 228 229#if !defined(CONFIG_PCI_PNP) 230 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 231 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 232 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 233#endif 234 235#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 236 237#endif /* CONFIG_PCI */ 238 239/* 240 * Environment 241 */ 242#define CONFIG_ENV_ADDR \ 243 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 244#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 245#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 246#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 247#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 248 249#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 250#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 251 252/* 253 * BOOTP options 254 */ 255#define CONFIG_BOOTP_BOOTFILESIZE 256 257/* 258 * Miscellaneous configurable options 259 */ 260#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 261 262#undef CONFIG_WATCHDOG /* watchdog disabled */ 263 264/* 265 * For booting Linux, the board info and command line data 266 * have to be in the first 256 MB of memory, since this is 267 * the maximum mapped by the Linux kernel during initialization. 268 */ 269 /* Initial Memory map for Linux */ 270#define CONFIG_SYS_BOOTMAPSZ (256 << 20) 271 272#define CONFIG_SYS_HRCW_LOW (\ 273 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 274 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 275 HRCWL_CSB_TO_CLKIN_4X1 |\ 276 HRCWL_VCO_1X2 |\ 277 HRCWL_CORE_TO_CSB_2X1) 278 279#if defined(PCI_64BIT) 280#define CONFIG_SYS_HRCW_HIGH (\ 281 HRCWH_PCI_HOST |\ 282 HRCWH_64_BIT_PCI |\ 283 HRCWH_PCI1_ARBITER_ENABLE |\ 284 HRCWH_PCI2_ARBITER_DISABLE |\ 285 HRCWH_CORE_ENABLE |\ 286 HRCWH_FROM_0X00000100 |\ 287 HRCWH_BOOTSEQ_DISABLE |\ 288 HRCWH_SW_WATCHDOG_DISABLE |\ 289 HRCWH_ROM_LOC_LOCAL_16BIT |\ 290 HRCWH_TSEC1M_IN_GMII |\ 291 HRCWH_TSEC2M_IN_GMII) 292#else 293#define CONFIG_SYS_HRCW_HIGH (\ 294 HRCWH_PCI_HOST |\ 295 HRCWH_32_BIT_PCI |\ 296 HRCWH_PCI1_ARBITER_ENABLE |\ 297 HRCWH_PCI2_ARBITER_DISABLE |\ 298 HRCWH_CORE_ENABLE |\ 299 HRCWH_FROM_0X00000100 |\ 300 HRCWH_BOOTSEQ_DISABLE |\ 301 HRCWH_SW_WATCHDOG_DISABLE |\ 302 HRCWH_ROM_LOC_LOCAL_16BIT |\ 303 HRCWH_TSEC1M_IN_GMII |\ 304 HRCWH_TSEC2M_IN_GMII) 305#endif 306 307/* System IO Config */ 308#define CONFIG_SYS_SICRH 0 309#define CONFIG_SYS_SICRL SICRL_LDP_A 310 311/* i-cache and d-cache disabled */ 312#define CONFIG_SYS_HID0_INIT 0x000000000 313#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 314 HID0_ENABLE_INSTRUCTION_CACHE) 315#define CONFIG_SYS_HID2 HID2_HBE 316 317#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 318 319/* DDR 0 - 512M */ 320#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 321 | BATL_PP_RW \ 322 | BATL_MEMCOHERENCE) 323#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 324 | BATU_BL_256M \ 325 | BATU_VS \ 326 | BATU_VP) 327#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 328 | BATL_PP_RW \ 329 | BATL_MEMCOHERENCE) 330#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 331 | BATU_BL_256M \ 332 | BATU_VS \ 333 | BATU_VP) 334 335/* stack in DCACHE @ 512M (no backing mem) */ 336#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 337 | BATL_PP_RW \ 338 | BATL_MEMCOHERENCE) 339#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 340 | BATU_BL_128K \ 341 | BATU_VS \ 342 | BATU_VP) 343 344/* PCI */ 345#ifdef CONFIG_PCI 346#define CONFIG_PCI_INDIRECT_BRIDGE 347#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 348 | BATL_PP_RW \ 349 | BATL_MEMCOHERENCE) 350#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 351 | BATU_BL_256M \ 352 | BATU_VS \ 353 | BATU_VP) 354#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 355 | BATL_PP_RW \ 356 | BATL_MEMCOHERENCE \ 357 | BATL_GUARDEDSTORAGE) 358#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 359 | BATU_BL_256M \ 360 | BATU_VS \ 361 | BATU_VP) 362#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 363 | BATL_PP_RW \ 364 | BATL_CACHEINHIBIT \ 365 | BATL_GUARDEDSTORAGE) 366#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 367 | BATU_BL_16M \ 368 | BATU_VS \ 369 | BATU_VP) 370#else 371#define CONFIG_SYS_IBAT3L (0) 372#define CONFIG_SYS_IBAT3U (0) 373#define CONFIG_SYS_IBAT4L (0) 374#define CONFIG_SYS_IBAT4U (0) 375#define CONFIG_SYS_IBAT5L (0) 376#define CONFIG_SYS_IBAT5U (0) 377#endif 378 379/* IMMRBAR */ 380#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 381 | BATL_PP_RW \ 382 | BATL_CACHEINHIBIT \ 383 | BATL_GUARDEDSTORAGE) 384#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 385 | BATU_BL_1M \ 386 | BATU_VS \ 387 | BATU_VP) 388 389/* FLASH */ 390#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 391 | BATL_PP_RW \ 392 | BATL_CACHEINHIBIT \ 393 | BATL_GUARDEDSTORAGE) 394#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 395 | BATU_BL_256M \ 396 | BATU_VS \ 397 | BATU_VP) 398 399#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 400#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 401#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 402#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 403#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 404#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 405#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 406#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 407#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 408#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 409#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 410#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 411#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 412#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 413#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 414#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 415 416#if defined(CONFIG_CMD_KGDB) 417#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 418#endif 419 420/* 421 * Environment Configuration 422 */ 423 424 /* default location for tftp and bootm */ 425#define CONFIG_LOADADDR 400000 426 427#define CONFIG_PREBOOT "echo;" \ 428 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 429 "echo" 430 431#define CONFIG_EXTRA_ENV_SETTINGS \ 432 "netdev=eth0\0" \ 433 "hostname=tqm834x\0" \ 434 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 435 "nfsroot=${serverip}:${rootpath}\0" \ 436 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 437 "addip=setenv bootargs ${bootargs} " \ 438 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 439 ":${hostname}:${netdev}:off panic=1\0" \ 440 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 441 "flash_nfs_old=run nfsargs addip addcons;" \ 442 "bootm ${kernel_addr}\0" \ 443 "flash_nfs=run nfsargs addip addcons;" \ 444 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 445 "flash_self_old=run ramargs addip addcons;" \ 446 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 447 "flash_self=run ramargs addip addcons;" \ 448 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 449 "net_nfs_old=tftp 400000 ${bootfile};" \ 450 "run nfsargs addip addcons;bootm\0" \ 451 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 452 "tftp ${fdt_addr_r} ${fdt_file}; " \ 453 "run nfsargs addip addcons; " \ 454 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 455 "rootpath=/opt/eldk/ppc_6xx\0" \ 456 "bootfile=tqm834x/uImage\0" \ 457 "fdtfile=tqm834x/tqm834x.dtb\0" \ 458 "kernel_addr_r=400000\0" \ 459 "fdt_addr_r=600000\0" \ 460 "ramdisk_addr_r=800000\0" \ 461 "kernel_addr=800C0000\0" \ 462 "fdt_addr=800A0000\0" \ 463 "ramdisk_addr=80300000\0" \ 464 "u-boot=tqm834x/u-boot.bin\0" \ 465 "load=tftp 200000 ${u-boot}\0" \ 466 "update=protect off 80000000 +${filesize};" \ 467 "era 80000000 +${filesize};" \ 468 "cp.b 200000 80000000 ${filesize}\0" \ 469 "upd=run load update\0" \ 470 "" 471 472#define CONFIG_BOOTCOMMAND "run flash_self" 473 474/* 475 * JFFS2 partitions 476 */ 477/* mtdparts command line support */ 478#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 479#define CONFIG_FLASH_CFI_MTD 480 481/* default mtd partition table */ 482#endif /* __CONFIG_H */ 483