1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __LS1043AQDS_H__ 7#define __LS1043AQDS_H__ 8 9#include "ls1043a_common.h" 10 11#ifndef __ASSEMBLY__ 12unsigned long get_board_sys_clk(void); 13unsigned long get_board_ddr_clk(void); 14#endif 15 16#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19#define CONFIG_SKIP_LOWLEVEL_INIT 20 21#define CONFIG_LAYERSCAPE_NS_ACCESS 22 23#define CONFIG_DIMM_SLOTS_PER_CTLR 1 24/* Physical Memory Map */ 25#define CONFIG_CHIP_SELECTS_PER_CTRL 4 26#define CONFIG_NR_DRAM_BANKS 2 27 28#define CONFIG_DDR_SPD 29#define SPD_EEPROM_ADDRESS 0x51 30#define CONFIG_SYS_SPD_BUS_NUM 0 31 32#ifndef CONFIG_SPL 33#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 34#endif 35 36#define CONFIG_DDR_ECC 37#ifdef CONFIG_DDR_ECC 38#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 39#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 40#endif 41 42#ifdef CONFIG_SYS_DPAA_FMAN 43#define CONFIG_FMAN_ENET 44#define CONFIG_PHY_VITESSE 45#define CONFIG_PHY_REALTEK 46#define CONFIG_PHYLIB_10G 47#define RGMII_PHY1_ADDR 0x1 48#define RGMII_PHY2_ADDR 0x2 49#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 50#define SGMII_CARD_PORT2_PHY_ADDR 0x1D 51#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 52#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 53/* PHY address on QSGMII riser card on slot 1 */ 54#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 55#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 56#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 57#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 58/* PHY address on QSGMII riser card on slot 2 */ 59#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 60#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 61#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 62#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 63#endif 64 65#ifdef CONFIG_RAMBOOT_PBL 66#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 67#endif 68 69#ifdef CONFIG_NAND_BOOT 70#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 71#endif 72 73#ifdef CONFIG_SD_BOOT 74#ifdef CONFIG_SD_BOOT_QSPI 75#define CONFIG_SYS_FSL_PBL_RCW \ 76 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 77#else 78#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 79#endif 80#endif 81 82/* LPUART */ 83#ifdef CONFIG_LPUART 84#define CONFIG_LPUART_32B_REG 85#endif 86 87/* SATA */ 88#define CONFIG_SCSI_AHCI_PLAT 89 90/* EEPROM */ 91#define CONFIG_ID_EEPROM 92#define CONFIG_SYS_I2C_EEPROM_NXID 93#define CONFIG_SYS_EEPROM_BUS_NUM 0 94#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 95#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 96#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 97#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 98 99#define CONFIG_SYS_SATA AHCI_BASE_ADDR 100 101#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 102#define CONFIG_SYS_SCSI_MAX_LUN 1 103#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 104 CONFIG_SYS_SCSI_MAX_LUN) 105 106/* 107 * IFC Definitions 108 */ 109#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 110#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 111#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 112 CSPR_PORT_SIZE_16 | \ 113 CSPR_MSEL_NOR | \ 114 CSPR_V) 115#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 116#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 117 + 0x8000000) | \ 118 CSPR_PORT_SIZE_16 | \ 119 CSPR_MSEL_NOR | \ 120 CSPR_V) 121#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 122 123#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 124 CSOR_NOR_TRHZ_80) 125#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 126 FTIM0_NOR_TEADC(0x5) | \ 127 FTIM0_NOR_TEAHC(0x5)) 128#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 129 FTIM1_NOR_TRAD_NOR(0x1a) | \ 130 FTIM1_NOR_TSEQRAD_NOR(0x13)) 131#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 132 FTIM2_NOR_TCH(0x4) | \ 133 FTIM2_NOR_TWPH(0xe) | \ 134 FTIM2_NOR_TWP(0x1c)) 135#define CONFIG_SYS_NOR_FTIM3 0 136 137#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 138#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 139#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 140#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 141 142#define CONFIG_SYS_FLASH_EMPTY_INFO 143#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 144 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 145 146#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 147#define CONFIG_SYS_WRITE_SWAPPED_DATA 148 149/* 150 * NAND Flash Definitions 151 */ 152#define CONFIG_NAND_FSL_IFC 153 154#define CONFIG_SYS_NAND_BASE 0x7e800000 155#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 156 157#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 158 159#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 160 | CSPR_PORT_SIZE_8 \ 161 | CSPR_MSEL_NAND \ 162 | CSPR_V) 163#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 164#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 165 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 166 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 167 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 168 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 169 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 170 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 171 172#define CONFIG_SYS_NAND_ONFI_DETECTION 173 174#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 175 FTIM0_NAND_TWP(0x18) | \ 176 FTIM0_NAND_TWCHT(0x7) | \ 177 FTIM0_NAND_TWH(0xa)) 178#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 179 FTIM1_NAND_TWBE(0x39) | \ 180 FTIM1_NAND_TRR(0xe) | \ 181 FTIM1_NAND_TRP(0x18)) 182#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 183 FTIM2_NAND_TREH(0xa) | \ 184 FTIM2_NAND_TWHRE(0x1e)) 185#define CONFIG_SYS_NAND_FTIM3 0x0 186 187#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 188#define CONFIG_SYS_MAX_NAND_DEVICE 1 189#define CONFIG_MTD_NAND_VERIFY_WRITE 190 191#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 192#endif 193 194#ifdef CONFIG_NAND_BOOT 195#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 196#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 197#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 198#endif 199 200#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 201#define CONFIG_QIXIS_I2C_ACCESS 202#define CONFIG_SYS_I2C_EARLY_INIT 203#endif 204 205/* 206 * QIXIS Definitions 207 */ 208#define CONFIG_FSL_QIXIS 209 210#ifdef CONFIG_FSL_QIXIS 211#define QIXIS_BASE 0x7fb00000 212#define QIXIS_BASE_PHYS QIXIS_BASE 213#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 214#define QIXIS_LBMAP_SWITCH 6 215#define QIXIS_LBMAP_MASK 0x0f 216#define QIXIS_LBMAP_SHIFT 0 217#define QIXIS_LBMAP_DFLTBANK 0x00 218#define QIXIS_LBMAP_ALTBANK 0x04 219#define QIXIS_LBMAP_NAND 0x09 220#define QIXIS_LBMAP_SD 0x00 221#define QIXIS_LBMAP_SD_QSPI 0xff 222#define QIXIS_LBMAP_QSPI 0xff 223#define QIXIS_RCW_SRC_NAND 0x106 224#define QIXIS_RCW_SRC_SD 0x040 225#define QIXIS_RCW_SRC_QSPI 0x045 226#define QIXIS_RST_CTL_RESET 0x41 227#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 228#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 229#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 230 231#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 232#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 233 CSPR_PORT_SIZE_8 | \ 234 CSPR_MSEL_GPCM | \ 235 CSPR_V) 236#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 237#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 238 CSOR_NOR_NOR_MODE_AVD_NOR | \ 239 CSOR_NOR_TRHZ_80) 240 241/* 242 * QIXIS Timing parameters for IFC GPCM 243 */ 244#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 245 FTIM0_GPCM_TEADC(0x20) | \ 246 FTIM0_GPCM_TEAHC(0x10)) 247#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 248 FTIM1_GPCM_TRAD(0x1f)) 249#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 250 FTIM2_GPCM_TCH(0x8) | \ 251 FTIM2_GPCM_TWP(0xf0)) 252#define CONFIG_SYS_FPGA_FTIM3 0x0 253#endif 254 255#ifdef CONFIG_NAND_BOOT 256#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 257#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 258#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 259#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 260#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 261#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 262#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 263#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 264#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 265#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 266#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 267#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 268#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 269#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 270#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 271#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 272#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 273#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 274#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 275#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 276#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 277#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 278#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 279#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 280#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 281#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 282#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 283#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 284#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 285#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 286#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 287#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 288#else 289#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 290#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 291#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 292#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 293#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 294#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 295#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 296#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 297#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 298#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 299#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 300#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 301#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 302#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 303#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 304#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 305#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 306#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 307#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 308#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 309#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 310#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 311#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 312#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 313#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 314#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 315#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 316#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 317#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 318#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 319#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 320#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 321#endif 322 323/* 324 * I2C bus multiplexer 325 */ 326#define I2C_MUX_PCA_ADDR_PRI 0x77 327#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 328#define I2C_RETIMER_ADDR 0x18 329#define I2C_MUX_CH_DEFAULT 0x8 330#define I2C_MUX_CH_CH7301 0xC 331#define I2C_MUX_CH5 0xD 332#define I2C_MUX_CH7 0xF 333 334#define I2C_MUX_CH_VOL_MONITOR 0xa 335 336/* Voltage monitor on channel 2*/ 337#define I2C_VOL_MONITOR_ADDR 0x40 338#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 339#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 340#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 341 342#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 343#ifndef CONFIG_SPL_BUILD 344#define CONFIG_VID 345#endif 346#define CONFIG_VOL_MONITOR_IR36021_SET 347#define CONFIG_VOL_MONITOR_INA220 348/* The lowest and highest voltage allowed for LS1043AQDS */ 349#define VDD_MV_MIN 819 350#define VDD_MV_MAX 1212 351 352/* QSPI device */ 353#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 354#define CONFIG_FSL_QSPI 355#ifdef CONFIG_FSL_QSPI 356#define CONFIG_SPI_FLASH_SPANSION 357#define FSL_QSPI_FLASH_SIZE (1 << 24) 358#define FSL_QSPI_FLASH_NUM 2 359#endif 360#endif 361 362/* 363 * Miscellaneous configurable options 364 */ 365#define CONFIG_MISC_INIT_R 366 367#define CONFIG_SYS_MEMTEST_START 0x80000000 368#define CONFIG_SYS_MEMTEST_END 0x9fffffff 369 370#define CONFIG_SYS_HZ 1000 371 372#define CONFIG_SYS_INIT_SP_OFFSET \ 373 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 374 375#ifdef CONFIG_SPL_BUILD 376#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 377#else 378#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 379#endif 380 381/* 382 * Environment 383 */ 384#define CONFIG_ENV_OVERWRITE 385 386#ifdef CONFIG_NAND_BOOT 387#define CONFIG_ENV_SIZE 0x2000 388#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 389#elif defined(CONFIG_SD_BOOT) 390#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 391#define CONFIG_SYS_MMC_ENV_DEV 0 392#define CONFIG_ENV_SIZE 0x2000 393#elif defined(CONFIG_QSPI_BOOT) 394#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 395#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 396#define CONFIG_ENV_SECT_SIZE 0x10000 397#else 398#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 399#define CONFIG_ENV_SECT_SIZE 0x20000 400#define CONFIG_ENV_SIZE 0x20000 401#endif 402 403#define CONFIG_CMDLINE_TAG 404 405#include <asm/fsl_secure_boot.h> 406 407#endif /* __LS1043AQDS_H__ */ 408