LXR uboot/include/configs/omapl138

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4 *
   5 * Based on davinci_dvevm.h. Original Copyrights follow:
   6 *
   7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8 */
   9
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13/*
  14 * Board
  15 */
  16#define CONFIG_DRIVER_TI_EMAC
  17#undef CONFIG_USE_SPIFLASH
  18#undef  CONFIG_SYS_USE_NOR
  19#define CONFIG_USE_NAND
  20
  21/*
  22* Disable DM_* for SPL build and can be re-enabled after adding
  23* DM support in SPL
  24*/
  25#ifdef CONFIG_SPL_BUILD
  26#undef CONFIG_DM_I2C
  27#undef CONFIG_DM_I2C_COMPAT
  28#endif
  29/*
  30 * SoC Configuration
  31 */
  32#define CONFIG_MACH_OMAPL138_LCDK
  33#define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  34#define CONFIG_SYS_OSCIN_FREQ           24000000
  35#define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  36#define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  37#define CONFIG_SYS_HZ                   1000
  38#define CONFIG_SKIP_LOWLEVEL_INIT
  39
  40/*
  41 * Memory Info
  42 */
  43#define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  44#define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  45#define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
  46#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  47
  48/* memtest start addr */
  49#define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  50
  51/* memtest will be run on 16MB */
  52#define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  53
  54#define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  55
  56#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  57        DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  58        DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  59        DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  60        DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  61        DAVINCI_SYSCFG_SUSPSRC_I2C)
  62
  63/*
  64 * PLL configuration
  65 */
  66
  67/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  68#define CONFIG_SYS_DA850_PLL0_PLLM     18
  69#define CONFIG_SYS_DA850_PLL1_PLLM     21
  70
  71/*
  72 * DDR2 memory configuration
  73 */
  74#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  75                                        DV_DDR_PHY_EXT_STRBEN | \
  76                                        (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  77
  78#define CONFIG_SYS_DA850_DDR2_SDBCR (             \
  79        (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
  80        (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
  81        (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
  82        (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
  83        (4 << DV_DDR_SDCR_CL_SHIFT)             | \
  84        (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
  85        (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  86
  87/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  88#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  89
  90#define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
  91        (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
  92        (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
  93        (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
  94        (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
  95        (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
  96        (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
  97        (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
  98        (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  99
 100#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
 101        (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
 102        (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
 103        (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
 104        (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
 105        (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
 106        (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
 107        (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 108
 109#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
 110#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 111
 112/*
 113 * Serial Driver info
 114 */
 115#define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 116#if !defined(CONFIG_DM_SERIAL)
 117#define CONFIG_SYS_NS16550_SERIAL
 118#define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 119#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 120#define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 121#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 122#endif
 123
 124#define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 125#define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 126#define CONFIG_SF_DEFAULT_SPEED         30000000
 127#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 128
 129#ifdef CONFIG_USE_SPIFLASH
 130#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 131#define CONFIG_SYS_SPI_U_BOOT_SIZE      0x30000
 132#endif
 133
 134/*
 135 * I2C Configuration
 136 */
 137#define CONFIG_SYS_I2C_DAVINCI
 138#define CONFIG_SYS_DAVINCI_I2C_SPEED    25000
 139#define CONFIG_SYS_DAVINCI_I2C_SLAVE    10 /* Bogus, master-only in U-Boot */
 140#define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
 141
 142/*
 143 * Flash & Environment
 144 */
 145#ifdef CONFIG_USE_NAND
 146#define CONFIG_NAND_DAVINCI
 147#define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 148#define CONFIG_ENV_SIZE                 (128 << 9)
 149#define CONFIG_SYS_NAND_USE_FLASH_BBT
 150#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 151#define CONFIG_SYS_NAND_PAGE_2K
 152#define CONFIG_SYS_NAND_CS              3
 153#define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 154#define CONFIG_SYS_NAND_MASK_CLE        0x10
 155#define CONFIG_SYS_NAND_MASK_ALE        0x8
 156#undef CONFIG_SYS_NAND_HW_ECC
 157#define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 158#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 159#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 160#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 161#define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 162#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 163#define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 164#define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 165#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 166#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 167                                        CONFIG_SYS_NAND_U_BOOT_SIZE - \
 168                                        CONFIG_SYS_MALLOC_LEN -       \
 169                                        GENERATED_GBL_DATA_SIZE)
 170#define CONFIG_SYS_NAND_ECCPOS          {                               \
 171                                6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
 172                                22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 173                                38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 174                                54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
 175#define CONFIG_SYS_NAND_PAGE_COUNT      64
 176#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 177#define CONFIG_SYS_NAND_ECCSIZE         512
 178#define CONFIG_SYS_NAND_ECCBYTES        10
 179#define CONFIG_SYS_NAND_OOBSIZE         64
 180#define CONFIG_SPL_NAND_BASE
 181#define CONFIG_SPL_NAND_DRIVERS
 182#define CONFIG_SPL_NAND_ECC
 183#define CONFIG_SPL_NAND_LOAD
 184#endif
 185
 186#ifdef CONFIG_SYS_USE_NOR
 187#define CONFIG_FLASH_CFI_DRIVER
 188#define CONFIG_SYS_FLASH_CFI
 189#define CONFIG_SYS_FLASH_PROTECTION
 190#define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 191#define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 192#define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 193#define CONFIG_ENV_SIZE                 (128 << 10)
 194#define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 195#define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 196#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 197               + 3)
 198#define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 199#endif
 200
 201#ifdef CONFIG_USE_SPIFLASH
 202#define CONFIG_ENV_SIZE                 (64 << 10)
 203#define CONFIG_ENV_OFFSET               (256 << 10)
 204#define CONFIG_ENV_SECT_SIZE            (64 << 10)
 205#endif
 206
 207/*
 208 * Network & Ethernet Configuration
 209 */
 210#ifdef CONFIG_DRIVER_TI_EMAC
 211#define CONFIG_MII
 212#undef  CONFIG_DRIVER_TI_EMAC_USE_RMII
 213#define CONFIG_BOOTP_DEFAULT
 214#define CONFIG_BOOTP_DNS2
 215#define CONFIG_BOOTP_SEND_HOSTNAME
 216#define CONFIG_NET_RETRY_COUNT  10
 217#endif
 218
 219/*
 220 * U-Boot general configuration
 221 */
 222#define CONFIG_MISC_INIT_R
 223#define CONFIG_BOOTFILE         "zImage" /* Boot file name */
 224#define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 225#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 226#define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 227#define CONFIG_MX_CYCLIC
 228
 229/*
 230 * Linux Information
 231 */
 232#define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 233#define CONFIG_CMDLINE_TAG
 234#define CONFIG_REVISION_TAG
 235#define CONFIG_SETUP_MEMORY_TAGS
 236#define CONFIG_BOOTCOMMAND \
 237                "run envboot; " \
 238                "run mmcboot; "
 239
 240#define DEFAULT_LINUX_BOOT_ENV \
 241        "loadaddr=0xc0700000\0" \
 242        "fdtaddr=0xc0600000\0" \
 243        "scriptaddr=0xc0600000\0"
 244
 245#include <environment/ti/mmc.h>
 246
 247#define CONFIG_EXTRA_ENV_SETTINGS \
 248        DEFAULT_LINUX_BOOT_ENV \
 249        DEFAULT_MMC_TI_ARGS \
 250        "bootpart=0:2\0" \
 251        "bootdir=/boot\0" \
 252        "bootfile=zImage\0" \
 253        "fdtfile=da850-lcdk.dtb\0" \
 254        "boot_fdt=yes\0" \
 255        "boot_fit=0\0" \
 256        "console=ttyS2,115200n8\0"
 257
 258#ifdef CONFIG_CMD_BDI
 259#define CONFIG_CLOCKS
 260#endif
 261
 262#ifndef CONFIG_DRIVER_TI_EMAC
 263#endif
 264
 265#ifdef CONFIG_USE_NAND
 266#define CONFIG_MTD_DEVICE
 267#define CONFIG_MTD_PARTITIONS
 268#endif
 269
 270#if !defined(CONFIG_USE_NAND) && \
 271        !defined(CONFIG_SYS_USE_NOR) && \
 272        !defined(CONFIG_USE_SPIFLASH)
 273#define CONFIG_ENV_SIZE         (16 << 10)
 274#endif
 275
 276/* SD/MMC */
 277
 278#ifdef CONFIG_ENV_IS_IN_MMC
 279#undef CONFIG_ENV_SIZE
 280#undef CONFIG_ENV_OFFSET
 281#define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 282#define CONFIG_ENV_OFFSET       (51 << 9)       /* Sector 51 */
 283#endif
 284
 285#ifndef CONFIG_DIRECT_NOR_BOOT
 286/* defines for SPL */
 287#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 288                                                CONFIG_SYS_MALLOC_LEN)
 289#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 290#define CONFIG_SPL_STACK        0x8001ff00
 291#define CONFIG_SPL_TEXT_BASE    0x80000000
 292#define CONFIG_SPL_MAX_FOOTPRINT        32768
 293#define CONFIG_SPL_PAD_TO       32768
 294#endif
 295
 296/* additions for new relocation code, must added to all boards */
 297#define CONFIG_SYS_SDRAM_BASE           0xc0000000
 298#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 299                                        GENERATED_GBL_DATA_SIZE)
 300
 301#include <asm/arch/hardware.h>
 302
 303#endif /* __CONFIG_H */
 304