1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6/* 7 * Corenet DS style board configuration file 8 */ 9#ifndef __T4QDS_H 10#define __T4QDS_H 11 12/* High Level Configuration Options */ 13#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 14#define CONFIG_MP /* support multiple processors */ 15 16#ifndef CONFIG_RESET_VECTOR_ADDRESS 17#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 18#endif 19 20#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 21#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 22#define CONFIG_PCIE1 /* PCIE controller 1 */ 23#define CONFIG_PCIE2 /* PCIE controller 2 */ 24#define CONFIG_PCIE3 /* PCIE controller 3 */ 25#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 26#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 27 28#define CONFIG_SYS_SRIO 29#define CONFIG_SRIO1 /* SRIO port 1 */ 30#define CONFIG_SRIO2 /* SRIO port 2 */ 31 32#define CONFIG_ENV_OVERWRITE 33 34/* 35 * These can be toggled for performance analysis, otherwise use default. 36 */ 37#define CONFIG_SYS_CACHE_STASHING 38#define CONFIG_BTB /* toggle branch predition */ 39#ifdef CONFIG_DDR_ECC 40#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 41#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 42#endif 43 44#define CONFIG_ENABLE_36BIT_PHYS 45 46#define CONFIG_ADDR_MAP 47#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 48 49#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 50#define CONFIG_SYS_MEMTEST_END 0x00400000 51 52/* 53 * Config the L3 Cache as L3 SRAM 54 */ 55#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 56#define CONFIG_SYS_L3_SIZE (512 << 10) 57#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 58#ifdef CONFIG_RAMBOOT_PBL 59#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 60#endif 61#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 62#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 63#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 64#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 65 66#define CONFIG_SYS_DCSRBAR 0xf0000000 67#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 68 69/* 70 * DDR Setup 71 */ 72#define CONFIG_VERY_BIG_RAM 73#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76#define CONFIG_DIMM_SLOTS_PER_CTLR 2 77#define CONFIG_CHIP_SELECTS_PER_CTRL 4 78#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 79 80#define CONFIG_DDR_SPD 81 82/* 83 * IFC Definitions 84 */ 85#define CONFIG_SYS_FLASH_BASE 0xe0000000 86#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 87 88#ifdef CONFIG_SPL_BUILD 89#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 90#else 91#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 92#endif 93 94#define CONFIG_MISC_INIT_R 95 96#define CONFIG_HWCONFIG 97 98/* define to use L1 as initial stack */ 99#define CONFIG_L1_INIT_RAM 100#define CONFIG_SYS_INIT_RAM_LOCK 101#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 102#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 103#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 104/* The assembler doesn't like typecast */ 105#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 106 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 107 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 108#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 109 110#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 111 GENERATED_GBL_DATA_SIZE) 112#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 113 114#define CONFIG_SYS_MONITOR_LEN (768 * 1024) 115#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 116 117/* Serial Port - controlled on board with jumper J8 118 * open - index 2 119 * shorted - index 1 120 */ 121#define CONFIG_SYS_NS16550_SERIAL 122#define CONFIG_SYS_NS16550_REG_SIZE 1 123#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 124 125#define CONFIG_SYS_BAUDRATE_TABLE \ 126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 127 128#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 129#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 130#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 131#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 132 133/* I2C */ 134#define CONFIG_SYS_I2C 135#define CONFIG_SYS_I2C_FSL 136#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 137#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 138#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 139#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 140 141/* 142 * RapidIO 143 */ 144#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 145#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 146#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 147 148#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 149#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 150#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 151 152/* 153 * General PCI 154 * Memory space is mapped 1-1, but I/O space must start from 0. 155 */ 156 157/* controller 1, direct to uli, tgtid 3, Base address 20000 */ 158#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 159#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 160#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 161#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 162#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 163#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 164#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 165#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 166 167/* controller 2, Slot 2, tgtid 2, Base address 201000 */ 168#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 169#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 170#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 171#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 172#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 173#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 174#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 175#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 176 177/* controller 3, Slot 1, tgtid 1, Base address 202000 */ 178#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 179#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 180#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 181#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 182#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 183#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 184#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 185#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 186 187/* controller 4, Base address 203000 */ 188#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 189#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 190#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 191#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 192#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 193#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 194 195#ifdef CONFIG_PCI 196#define CONFIG_PCI_INDIRECT_BRIDGE 197 198#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 199#endif /* CONFIG_PCI */ 200 201/* SATA */ 202#ifdef CONFIG_FSL_SATA_V2 203#define CONFIG_SYS_SATA_MAX_DEVICE 2 204#define CONFIG_SATA1 205#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 206#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 207#define CONFIG_SATA2 208#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 209#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 210 211#define CONFIG_LBA48 212#endif 213 214#ifdef CONFIG_FMAN_ENET 215#define CONFIG_MII /* MII PHY management */ 216#define CONFIG_ETHPRIME "FM1@DTSEC1" 217#endif 218 219/* 220 * Environment 221 */ 222#define CONFIG_LOADS_ECHO /* echo on for serial download */ 223#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 224 225/* 226 * Command line configuration. 227 */ 228 229/* 230 * Miscellaneous configurable options 231 */ 232#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 233 234/* 235 * For booting Linux, the board info and command line data 236 * have to be in the first 64 MB of memory, since this is 237 * the maximum mapped by the Linux kernel during initialization. 238 */ 239#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 240#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 241 242#ifdef CONFIG_CMD_KGDB 243#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 244#endif 245 246/* 247 * Environment Configuration 248 */ 249#define CONFIG_ROOTPATH "/opt/nfsroot" 250#define CONFIG_BOOTFILE "uImage" 251#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 252 253/* default location for tftp and bootm */ 254#define CONFIG_LOADADDR 1000000 255 256#define CONFIG_HVBOOT \ 257 "setenv bootargs config-addr=0x60000000; " \ 258 "bootm 0x01000000 - 0x00f00000" 259 260#endif /* __CONFIG_H */ 261