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11#include <common.h>
12#include <div64.h>
13#include <netdev.h>
14#include <asm/io.h>
15#include <asm/arch-imx/cpu.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/clock.h>
18
19#ifdef CONFIG_FSL_ESDHC
20#include <fsl_esdhc.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23#endif
24
25
26
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29
30
31
32static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
33{
34 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
35 & CCM_PLL_MFI_MASK;
36 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
37 & CCM_PLL_MFN_MASK;
38 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
39 & CCM_PLL_MFD_MASK;
40 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
41 & CCM_PLL_PD_MASK;
42
43 mfi = mfi <= 5 ? 5 : mfi;
44 mfn = mfn >= 512 ? mfn - 1024 : mfn;
45 mfd += 1;
46 pd += 1;
47
48 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
49 mfd * pd);
50}
51
52static ulong imx_get_mpllclk(void)
53{
54 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
55 ulong fref = MXC_HCLK;
56
57 return imx_decode_pll(readl(&ccm->mpctl), fref);
58}
59
60static ulong imx_get_upllclk(void)
61{
62 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
63 ulong fref = MXC_HCLK;
64
65 return imx_decode_pll(readl(&ccm->upctl), fref);
66}
67
68static ulong imx_get_armclk(void)
69{
70 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
71 ulong cctl = readl(&ccm->cctl);
72 ulong fref = imx_get_mpllclk();
73 ulong div;
74
75 if (cctl & CCM_CCTL_ARM_SRC)
76 fref = lldiv((u64) fref * 3, 4);
77
78 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
79 & CCM_CCTL_ARM_DIV_MASK) + 1;
80
81 return fref / div;
82}
83
84static ulong imx_get_ahbclk(void)
85{
86 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
87 ulong cctl = readl(&ccm->cctl);
88 ulong fref = imx_get_armclk();
89 ulong div;
90
91 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
92 & CCM_CCTL_AHB_DIV_MASK) + 1;
93
94 return fref / div;
95}
96
97static ulong imx_get_ipgclk(void)
98{
99 return imx_get_ahbclk() / 2;
100}
101
102static ulong imx_get_perclk(int clk)
103{
104 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
105 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
106 imx_get_ahbclk();
107 ulong div;
108
109 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
110 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
111
112 return fref / div;
113}
114
115int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
116{
117 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
118 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
119 ulong div = (fref + freq - 1) / freq;
120
121 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
122 return -EINVAL;
123
124 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
125 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
126 div << CCM_PERCLK_SHIFT(clk));
127 if (from_upll)
128 setbits_le32(&ccm->mcr, 1 << clk);
129 else
130 clrbits_le32(&ccm->mcr, 1 << clk);
131 return 0;
132}
133
134unsigned int mxc_get_clock(enum mxc_clock clk)
135{
136 if (clk >= MXC_CLK_NUM)
137 return -1;
138 switch (clk) {
139 case MXC_ARM_CLK:
140 return imx_get_armclk();
141 case MXC_AHB_CLK:
142 return imx_get_ahbclk();
143 case MXC_IPG_CLK:
144 case MXC_CSPI_CLK:
145 case MXC_FEC_CLK:
146 return imx_get_ipgclk();
147 default:
148 return imx_get_perclk(clk);
149 }
150}
151
152u32 get_cpu_rev(void)
153{
154 u32 srev;
155 u32 system_rev = 0x25000;
156
157
158 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
159 srev = readl(&iim->iim_srev);
160
161 switch (srev) {
162 case 0x00:
163 system_rev |= CHIP_REV_1_0;
164 break;
165 case 0x01:
166 system_rev |= CHIP_REV_1_1;
167 break;
168 case 0x02:
169 system_rev |= CHIP_REV_1_2;
170 break;
171 default:
172 system_rev |= 0x8000;
173 break;
174 }
175
176 return system_rev;
177}
178
179#if defined(CONFIG_DISPLAY_CPUINFO)
180static char *get_reset_cause(void)
181{
182
183 struct ccm_regs *ccm =
184 (struct ccm_regs *)IMX_CCM_BASE;
185
186 u32 cause = readl(&ccm->rcsr) & 0x0f;
187
188 if (cause == 0)
189 return "POR";
190 else if (cause == 1)
191 return "RST";
192 else if ((cause & 2) == 2)
193 return "WDOG";
194 else if ((cause & 4) == 4)
195 return "SW RESET";
196 else if ((cause & 8) == 8)
197 return "JTAG";
198 else
199 return "unknown reset";
200
201}
202
203int print_cpuinfo(void)
204{
205 char buf[32];
206 u32 cpurev = get_cpu_rev();
207
208 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
209 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
210 ((cpurev & 0x8000) ? " unknown" : ""),
211 strmhz(buf, imx_get_armclk()));
212 printf("Reset cause: %s\n", get_reset_cause());
213 return 0;
214}
215#endif
216
217void enable_caches(void)
218{
219#ifndef CONFIG_SYS_DCACHE_OFF
220
221 dcache_enable();
222#endif
223}
224
225#if defined(CONFIG_FEC_MXC)
226
227
228
229
230int cpu_eth_init(bd_t *bis)
231{
232 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
233 ulong val;
234
235 val = readl(&ccm->cgr0);
236 val |= (1 << 23);
237 writel(val, &ccm->cgr0);
238 return fecmxc_initialize(bis);
239}
240#endif
241
242int get_clocks(void)
243{
244#ifdef CONFIG_FSL_ESDHC
245#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
246 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
247#else
248 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
249#endif
250#endif
251 return 0;
252}
253
254#ifdef CONFIG_FSL_ESDHC
255
256
257
258
259int cpu_mmc_init(bd_t *bis)
260{
261 return fsl_esdhc_mmc_init(bis);
262}
263#endif
264
265#ifdef CONFIG_FEC_MXC
266void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
267{
268 int i;
269 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
270 struct fuse_bank *bank = &iim->bank[0];
271 struct fuse_bank0_regs *fuse =
272 (struct fuse_bank0_regs *)bank->fuse_regs;
273
274 for (i = 0; i < 6; i++)
275 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
276}
277#endif
278
