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9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/macro.h>
12#include <asm/system.h>
13#include <linux/linkage.h>
14
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23
24.pushsection .text.__asm_dcache_level, "ax"
25ENTRY(__asm_dcache_level)
26 lsl x12, x0,
27 msr csselr_el1, x12
28 isb
29 mrs x6, ccsidr_el1
30 and x2, x6,
31 add x2, x2,
32 mov x3,
33 and x3, x3, x6, lsr
34 clz w5, w3
35 mov x4,
36 and x4, x4, x6, lsr
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38
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40
41
42
43loop_set:
44 mov x6, x3
45loop_way:
46 lsl x7, x6, x5
47 orr x9, x12, x7
48 lsl x7, x4, x2
49 orr x9, x9, x7
50 tbz w1,
51 dc isw, x9
52 b 2f
531: dc cisw, x9
542: subs x6, x6,
55 b.ge loop_way
56 subs x4, x4,
57 b.ge loop_set
58
59 ret
60ENDPROC(__asm_dcache_level)
61.popsection
62
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69
70.pushsection .text.__asm_dcache_all, "ax"
71ENTRY(__asm_dcache_all)
72 mov x1, x0
73 dsb sy
74 mrs x10, clidr_el1
75 lsr x11, x10,
76 and x11, x11,
77 cbz x11, finished
78 mov x15, lr
79 mov x0,
80
81
82
83
84
85loop_level:
86 lsl x12, x0,
87 add x12, x12, x0
88 lsr x12, x10, x12
89 and x12, x12,
90 cmp x12,
91 b.lt skip
92 bl __asm_dcache_level
93skip:
94 add x0, x0,
95 cmp x11, x0
96 b.gt loop_level
97
98 mov x0,
99 msr csselr_el1, x0
100 dsb sy
101 isb
102 mov lr, x15
103
104finished:
105 ret
106ENDPROC(__asm_dcache_all)
107.popsection
108
109.pushsection .text.__asm_flush_dcache_all, "ax"
110ENTRY(__asm_flush_dcache_all)
111 mov x0,
112 b __asm_dcache_all
113ENDPROC(__asm_flush_dcache_all)
114.popsection
115
116.pushsection .text.__asm_invalidate_dcache_all, "ax"
117ENTRY(__asm_invalidate_dcache_all)
118 mov x0,
119 b __asm_dcache_all
120ENDPROC(__asm_invalidate_dcache_all)
121.popsection
122
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130
131.pushsection .text.__asm_flush_dcache_range, "ax"
132ENTRY(__asm_flush_dcache_range)
133 mrs x3, ctr_el0
134 lsr x3, x3,
135 and x3, x3,
136 mov x2,
137 lsl x2, x2, x3
138
139
140 sub x3, x2,
141 bic x0, x0, x3
1421: dc civac, x0
143 add x0, x0, x2
144 cmp x0, x1
145 b.lo 1b
146 dsb sy
147 ret
148ENDPROC(__asm_flush_dcache_range)
149.popsection
150
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157
158.pushsection .text.__asm_invalidate_dcache_range, "ax"
159ENTRY(__asm_invalidate_dcache_range)
160 mrs x3, ctr_el0
161 ubfm x3, x3,
162 mov x2,
163 lsl x2, x2, x3
164
165
166 sub x3, x2,
167 bic x0, x0, x3
1681: dc ivac, x0
169 add x0, x0, x2
170 cmp x0, x1
171 b.lo 1b
172 dsb sy
173 ret
174ENDPROC(__asm_invalidate_dcache_range)
175.popsection
176
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181
182.pushsection .text.__asm_invalidate_icache_all, "ax"
183ENTRY(__asm_invalidate_icache_all)
184 ic ialluis
185 isb sy
186 ret
187ENDPROC(__asm_invalidate_icache_all)
188.popsection
189
190.pushsection .text.__asm_invalidate_l3_dcache, "ax"
191ENTRY(__asm_invalidate_l3_dcache)
192 mov x0,
193 ret
194ENDPROC(__asm_invalidate_l3_dcache)
195 .weak __asm_invalidate_l3_dcache
196.popsection
197
198.pushsection .text.__asm_flush_l3_dcache, "ax"
199ENTRY(__asm_flush_l3_dcache)
200 mov x0,
201 ret
202ENDPROC(__asm_flush_l3_dcache)
203 .weak __asm_flush_l3_dcache
204.popsection
205
206.pushsection .text.__asm_invalidate_l3_icache, "ax"
207ENTRY(__asm_invalidate_l3_icache)
208 mov x0,
209 ret
210ENDPROC(__asm_invalidate_l3_icache)
211 .weak __asm_invalidate_l3_icache
212.popsection
213
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219.pushsection .text.__asm_switch_ttbr, "ax"
220ENTRY(__asm_switch_ttbr)
221
222 switch_el x4, 3f, 2f, 1f
2233: mrs x2, sctlr_el3
224 b 0f
2252: mrs x2, sctlr_el2
226 b 0f
2271: mrs x2, sctlr_el1
2280:
229
230
231 movn x1,
232 and x1, x2, x1
233 switch_el x4, 3f, 2f, 1f
2343: msr sctlr_el3, x1
235 b 0f
2362: msr sctlr_el2, x1
237 b 0f
2381: msr sctlr_el1, x1
2390: isb
240
241
242 mov x3, x30
243 bl __asm_invalidate_tlb_all
244
245
246
247
248 switch_el x4, 3f, 2f, 1f
2493: msr ttbr0_el3, x0
250 b 0f
2512: msr ttbr0_el2, x0
252 b 0f
2531: msr ttbr0_el1, x0
2540: isb
255
256
257 switch_el x4, 3f, 2f, 1f
2583: msr sctlr_el3, x2
259 b 0f
2602: msr sctlr_el2, x2
261 b 0f
2621: msr sctlr_el1, x2
2630: isb
264
265 ret x3
266ENDPROC(__asm_switch_ttbr)
267.popsection
268