LXR uboot/arch/arm/include/asm/arch-rockchip/cru

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4 * Author: Andy Yan <andy.yan@rock-chips.com>
   5 */
   6#ifndef _ASM_ARCH_CRU_RK3368_H
   7#define _ASM_ARCH_CRU_RK3368_H
   8
   9#include <common.h>
  10
  11
  12/* RK3368 clock numbers */
  13enum rk3368_pll_id {
  14        APLLB,
  15        APLLL,
  16        DPLL,
  17        CPLL,
  18        GPLL,
  19        NPLL,
  20        PLL_COUNT,
  21};
  22
  23struct rk3368_cru {
  24        struct rk3368_pll {
  25                unsigned int con0;
  26                unsigned int con1;
  27                unsigned int con2;
  28                unsigned int con3;
  29        } pll[6];
  30        unsigned int reserved[0x28];
  31        unsigned int clksel_con[56];
  32        unsigned int reserved1[8];
  33        unsigned int clkgate_con[25];
  34        unsigned int reserved2[7];
  35        unsigned int glb_srst_fst_val;
  36        unsigned int glb_srst_snd_val;
  37        unsigned int reserved3[0x1e];
  38        unsigned int softrst_con[15];
  39        unsigned int reserved4[0x11];
  40        unsigned int misc_con;
  41        unsigned int glb_cnt_th;
  42        unsigned int glb_rst_con;
  43        unsigned int glb_rst_st;
  44        unsigned int reserved5[0x1c];
  45        unsigned int sdmmc_con[2];
  46        unsigned int sdio0_con[2];
  47        unsigned int sdio1_con[2];
  48        unsigned int emmc_con[2];
  49};
  50check_member(rk3368_cru, emmc_con[1], 0x41c);
  51
  52struct rk3368_clk_priv {
  53        struct rk3368_cru *cru;
  54};
  55
  56enum {
  57        /* PLL CON0 */
  58        PLL_NR_SHIFT                    = 8,
  59        PLL_NR_MASK                     = GENMASK(13, 8),
  60        PLL_OD_SHIFT                    = 0,
  61        PLL_OD_MASK                     = GENMASK(3, 0),
  62
  63        /* PLL CON1 */
  64        PLL_LOCK_STA                    = BIT(31),
  65        PLL_NF_SHIFT                    = 0,
  66        PLL_NF_MASK                     = GENMASK(12, 0),
  67
  68        /* PLL CON2 */
  69        PLL_BWADJ_SHIFT                 = 0,
  70        PLL_BWADJ_MASK                  = GENMASK(11, 0),
  71
  72        /* PLL CON3 */
  73        PLL_MODE_SHIFT                  = 8,
  74        PLL_MODE_MASK                   = GENMASK(9, 8),
  75        PLL_MODE_SLOW                   = 0,
  76        PLL_MODE_NORMAL                 = 1,
  77        PLL_MODE_DEEP_SLOW              = 3,
  78        PLL_RESET_SHIFT                 = 5,
  79        PLL_RESET                       = 1,
  80        PLL_RESET_MASK                  = GENMASK(5, 5),
  81
  82        /* CLKSEL12_CON */
  83        MCU_STCLK_DIV_SHIFT             = 8,
  84        MCU_STCLK_DIV_MASK              = GENMASK(10, 8),
  85        MCU_PLL_SEL_SHIFT               = 7,
  86        MCU_PLL_SEL_MASK                = BIT(7),
  87        MCU_PLL_SEL_CPLL                = 0,
  88        MCU_PLL_SEL_GPLL                = 1,
  89        MCU_CLK_DIV_SHIFT               = 0,
  90        MCU_CLK_DIV_MASK                = GENMASK(4, 0),
  91
  92        /* CLKSEL_CON25 */
  93        CLK_SARADC_DIV_CON_SHIFT        = 8,
  94        CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
  95        CLK_SARADC_DIV_CON_WIDTH        = 8,
  96
  97        /* CLKSEL43_CON */
  98        GMAC_DIV_CON_SHIFT              = 0x0,
  99        GMAC_DIV_CON_MASK               = GENMASK(4, 0),
 100        GMAC_PLL_SHIFT                  = 6,
 101        GMAC_PLL_MASK                   = GENMASK(7, 6),
 102        GMAC_PLL_SELECT_NEW             = (0x0 << GMAC_PLL_SHIFT),
 103        GMAC_PLL_SELECT_CODEC           = (0x1 << GMAC_PLL_SHIFT),
 104        GMAC_PLL_SELECT_GENERAL         = (0x2 << GMAC_PLL_SHIFT),
 105        GMAC_MUX_SEL_EXTCLK             = BIT(8),
 106
 107        /* CLKSEL51_CON */
 108        MMC_PLL_SEL_SHIFT               = 8,
 109        MMC_PLL_SEL_MASK                = GENMASK(9, 8),
 110        MMC_PLL_SEL_CPLL                = (0 << MMC_PLL_SEL_SHIFT),
 111        MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
 112        MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
 113        MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
 114        MMC_CLK_DIV_SHIFT               = 0,
 115        MMC_CLK_DIV_MASK                = GENMASK(6, 0),
 116
 117        /* SOFTRST1_CON */
 118        MCU_PO_SRST_MASK                = BIT(13),
 119        MCU_SYS_SRST_MASK               = BIT(12),
 120        DMA1_SRST_REQ                   = BIT(2),
 121
 122        /* SOFTRST4_CON */
 123        DMA2_SRST_REQ                   = BIT(0),
 124
 125        /* GLB_RST_CON */
 126        PMU_GLB_SRST_CTRL_SHIFT         = 2,
 127        PMU_GLB_SRST_CTRL_MASK          = GENMASK(3, 2),
 128        PMU_RST_BY_FST_GLB_SRST         = 0,
 129        PMU_RST_BY_SND_GLB_SRST         = 1,
 130        PMU_RST_DISABLE                 = 2,
 131        WDT_GLB_SRST_CTRL_SHIFT         = 1,
 132        WDT_GLB_SRST_CTRL_MASK          = BIT(1),
 133        WDT_TRIGGER_SND_GLB_SRST        = 0,
 134        WDT_TRIGGER_FST_GLB_SRST        = 1,
 135        TSADC_GLB_SRST_CTRL_SHIFT       = 0,
 136        TSADC_GLB_SRST_CTRL_MASK        = BIT(0),
 137        TSADC_TRIGGER_SND_GLB_SRST      = 0,
 138        TSADC_TRIGGER_FST_GLB_SRST      = 1,
 139
 140};
 141#endif
 142