LXR uboot/arch/arm/include/asm/mach-imx/sys

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2009
   4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   5 */
   6
   7#ifndef _SYS_PROTO_H_
   8#define _SYS_PROTO_H_
   9
  10#include <asm/io.h>
  11#include <asm/mach-imx/regs-common.h>
  12#include <common.h>
  13#include "../arch-imx/cpu.h"
  14
  15#define soc_rev() (get_cpu_rev() & 0xFF)
  16#define is_soc_rev(rev) (soc_rev() == rev)
  17
  18/* returns MXC_CPU_ value */
  19#define cpu_type(rev) (((rev) >> 12) & 0xff)
  20#define soc_type(rev) (((rev) >> 12) & 0xf0)
  21/* both macros return/take MXC_CPU_ constants */
  22#define get_cpu_type() (cpu_type(get_cpu_rev()))
  23#define get_soc_type() (soc_type(get_cpu_rev()))
  24#define is_cpu_type(cpu) (get_cpu_type() == cpu)
  25#define is_soc_type(soc) (get_soc_type() == soc)
  26
  27#define is_mx6() (is_soc_type(MXC_SOC_MX6))
  28#define is_mx7() (is_soc_type(MXC_SOC_MX7))
  29#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
  30
  31#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
  32#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
  33#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
  34#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
  35#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
  36#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
  37#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
  38#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
  39#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
  40#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
  41
  42#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
  43
  44#ifdef CONFIG_MX6
  45#define IMX6_SRC_GPR10_BMODE            BIT(28)
  46
  47#define IMX6_BMODE_MASK                 GENMASK(7, 0)
  48#define IMX6_BMODE_SHIFT                4
  49#define IMX6_BMODE_EMI_MASK             BIT(3)
  50#define IMX6_BMODE_EMI_SHIFT            3
  51#define IMX6_BMODE_SERIAL_ROM_MASK      GENMASK(26, 24)
  52#define IMX6_BMODE_SERIAL_ROM_SHIFT     24
  53
  54enum imx6_bmode_serial_rom {
  55        IMX6_BMODE_ECSPI1,
  56        IMX6_BMODE_ECSPI2,
  57        IMX6_BMODE_ECSPI3,
  58        IMX6_BMODE_ECSPI4,
  59        IMX6_BMODE_ECSPI5,
  60        IMX6_BMODE_I2C1,
  61        IMX6_BMODE_I2C2,
  62        IMX6_BMODE_I2C3,
  63};
  64
  65enum imx6_bmode_emi {
  66        IMX6_BMODE_ONENAND,
  67        IMX6_BMODE_NOR,
  68};
  69
  70enum imx6_bmode {
  71        IMX6_BMODE_EMI,
  72#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  73        IMX6_BMODE_QSPI,
  74        IMX6_BMODE_RESERVED,
  75#else
  76        IMX6_BMODE_RESERVED,
  77        IMX6_BMODE_SATA,
  78#endif
  79        IMX6_BMODE_SERIAL_ROM,
  80        IMX6_BMODE_SD,
  81        IMX6_BMODE_ESD,
  82        IMX6_BMODE_MMC,
  83        IMX6_BMODE_EMMC,
  84        IMX6_BMODE_NAND_MIN,
  85        IMX6_BMODE_NAND_MAX = 0xf,
  86};
  87
  88static inline u8 imx6_is_bmode_from_gpr9(void)
  89{
  90        return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
  91}
  92
  93u32 imx6_src_get_boot_mode(void);
  94void gpr_init(void);
  95
  96#endif /* CONFIG_MX6 */
  97
  98u32 get_nr_cpus(void);
  99u32 get_cpu_rev(void);
 100u32 get_cpu_speed_grade_hz(void);
 101u32 get_cpu_temp_grade(int *minc, int *maxc);
 102const char *get_imx_type(u32 imxtype);
 103u32 imx_ddr_size(void);
 104void sdelay(unsigned long);
 105void set_chipselect_size(int const);
 106
 107void init_aips(void);
 108void init_src(void);
 109void init_snvs(void);
 110void imx_wdog_disable_powerdown(void);
 111
 112int board_mmc_get_env_dev(int devno);
 113
 114int nxp_board_rev(void);
 115char nxp_board_rev_string(void);
 116
 117/*
 118 * Initializes on-chip ethernet controllers.
 119 * to override, implement board_eth_init()
 120 */
 121int fecmxc_initialize(bd_t *bis);
 122u32 get_ahb_clk(void);
 123u32 get_periph_clk(void);
 124
 125void lcdif_power_down(void);
 126
 127int mxs_reset_block(struct mxs_register_32 *reg);
 128int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 129int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 130
 131unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 132                           unsigned long reg1, unsigned long reg2);
 133#endif
 134