LXR uboot/arch/arm/mach-omap2/omap-cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *
   4 * Common functions for OMAP4/5 based boards
   5 *
   6 * (C) Copyright 2010
   7 * Texas Instruments, <www.ti.com>
   8 *
   9 * Author :
  10 *      Aneesh V        <aneesh@ti.com>
  11 *      Steve Sakoman   <steve@sakoman.com>
  12 */
  13
  14#include <common.h>
  15#include <asm/cache.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19/*
  20 * Without LPAE short descriptors are used
  21 * Set C - Cache Bit3
  22 * Set B - Buffer Bit2
  23 * The last 2 bits set to 0b10
  24 * Do Not set XN bit4
  25 * So value is 0xe
  26 *
  27 * With LPAE cache configuration happens via MAIR0 register
  28 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
  29 * 0xFF maps to Cache writeback with Read and Write Allocate set
  30 * The bits[1:0] should have the value 0b01 for the first level
  31 * descriptor.
  32 * So the value is 0xd
  33 */
  34
  35#ifdef CONFIG_ARMV7_LPAE
  36#define ARMV7_DCACHE_POLICY     DCACHE_WRITEALLOC
  37#else
  38#define ARMV7_DCACHE_POLICY     DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
  39#endif
  40
  41#define ARMV7_DOMAIN_CLIENT     1
  42#define ARMV7_DOMAIN_MASK       (0x3 << 0)
  43
  44void enable_caches(void)
  45{
  46
  47        /* Enable I cache if not enabled */
  48        if (!icache_status())
  49                icache_enable();
  50
  51        dcache_enable();
  52}
  53
  54void dram_bank_mmu_setup(int bank)
  55{
  56        bd_t *bd = gd->bd;
  57        int     i;
  58
  59        u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  60        u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
  61        u32 end = start + size;
  62
  63        debug("%s: bank: %d\n", __func__, bank);
  64        for (i = start; i < end; i++)
  65                set_section_dcache(i, ARMV7_DCACHE_POLICY);
  66}
  67
  68void arm_init_domains(void)
  69{
  70        u32 reg;
  71
  72        reg = get_dacr();
  73        /*
  74        * Set DOMAIN to client access so that all permissions
  75        * set in pagetables are validated by the mmu.
  76        */
  77        reg &= ~ARMV7_DOMAIN_MASK;
  78        reg |= ARMV7_DOMAIN_CLIENT;
  79        set_dacr(reg);
  80}
  81