LXR uboot/arch/sh/include/asm/cpu

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2008, 2011 Renesas Solutions Corp.
   4 *
   5 * SH7724 Internal I/O register
   6 */
   7
   8#ifndef _ASM_CPU_SH7724_H_
   9#define _ASM_CPU_SH7724_H_
  10
  11#define CACHE_OC_NUM_WAYS       4
  12#define CCR_CACHE_INIT  0x0000090d
  13
  14/* EXP */
  15#define TRA             0xFF000020
  16#define EXPEVT  0xFF000024
  17#define INTEVT  0xFF000028
  18
  19/* MMU */
  20#define PTEH    0xFF000000
  21#define PTEL    0xFF000004
  22#define TTB             0xFF000008
  23#define TEA             0xFF00000C
  24#define MMUCR   0xFF000010
  25#define PASCR   0xFF000070
  26#define IRMCR   0xFF000078
  27
  28/* CACHE */
  29#define CCR             0xFF00001C
  30#define RAMCR   0xFF000074
  31
  32/* INTC */
  33
  34/* BSC */
  35#define MMSELR          0xFF800020
  36#define CMNCR           0xFEC10000
  37#define CS0BCR          0xFEC10004
  38#define CS2BCR          0xFEC10008
  39#define CS4BCR          0xFEC10010
  40#define CS5ABCR         0xFEC10014
  41#define CS5BBCR         0xFEC10018
  42#define CS6ABCR         0xFEC1001C
  43#define CS6BBCR         0xFEC10020
  44#define CS0WCR          0xFEC10024
  45#define CS2WCR          0xFEC10028
  46#define CS4WCR          0xFEC10030
  47#define CS5AWCR         0xFEC10034
  48#define CS5BWCR         0xFEC10038
  49#define CS6AWCR         0xFEC1003C
  50#define CS6BWCR         0xFEC10040
  51#define RBWTCNT         0xFEC10054
  52
  53/* SBSC */
  54#define SBSC_SDCR       0xFE400008
  55#define SBSC_SDWCR      0xFE40000C
  56#define SBSC_SDPCR      0xFE400010
  57#define SBSC_RTCSR      0xFE400014
  58#define SBSC_RTCNT      0xFE400018
  59#define SBSC_RTCOR      0xFE40001C
  60#define SBSC_RFCR       0xFE400020
  61
  62/* DSBC */
  63#define DBKIND          0xFD000008
  64#define DBSTATE         0xFD00000C
  65#define DBEN            0xFD000010
  66#define DBCMDCNT        0xFD000014
  67#define DBCKECNT        0xFD000018
  68#define DBCONF          0xFD000020
  69#define DBTR0           0xFD000030
  70#define DBTR1           0xFD000034
  71#define DBTR2           0xFD000038
  72#define DBTR3           0xFD00003C
  73#define DBRFPDN0        0xFD000040
  74#define DBRFPDN1        0xFD000044
  75#define DBRFPDN2        0xFD000048
  76#define DBRFSTS         0xFD00004C
  77#define DBMRCNT         0xFD000060
  78#define DBPDCNT0        0xFD000108
  79
  80/* DMAC */
  81
  82/* CPG */
  83#define FRQCRA          0xA4150000
  84#define FRQCRB          0xA4150004
  85#define FRQCR           FRQCRA
  86#define VCLKCR      0xA4150004
  87#define SCLKACR     0xA4150008
  88#define SCLKBCR     0xA415000C
  89#define IRDACLKCR   0xA4150018
  90#define PLLCR       0xA4150024
  91#define DLLFRQ      0xA4150050
  92
  93/* LOW POWER MODE */
  94#define STBCR       0xA4150020
  95#define MSTPCR0     0xA4150030
  96#define MSTPCR1     0xA4150034
  97#define MSTPCR2     0xA4150038
  98
  99/* RWDT */
 100#define RWTCNT      0xA4520000
 101#define RWTCSR      0xA4520004
 102#define WTCNT           RWTCNT
 103
 104/* TMU */
 105#define TMU_BASE        0xFFD80000
 106
 107/* TPU */
 108
 109/* CMT */
 110#define CMSTR       0xA44A0000
 111#define CMCSR       0xA44A0060
 112#define CMCNT       0xA44A0064
 113#define CMCOR       0xA44A0068
 114
 115/* MSIOF */
 116
 117/* SCIF */
 118#define SCIF0_BASE  0xFFE00000
 119#define SCIF1_BASE  0xFFE10000
 120#define SCIF2_BASE  0xFFE20000
 121#define SCIF3_BASE  0xa4e30000
 122#define SCIF4_BASE  0xa4e40000
 123#define SCIF5_BASE  0xa4e50000
 124
 125/* RTC */
 126/* IrDA */
 127/* KEYSC */
 128/* USB */
 129/* IIC */
 130/* FLCTL */
 131/* VPU */
 132/* VIO(CEU) */
 133/* VIO(VEU) */
 134/* VIO(BEU) */
 135/* 2DG */
 136/* LCDC */
 137/* VOU */
 138/* TSIF */
 139/* SIU */
 140/* ATAPI */
 141
 142/* PFC */
 143#define PACR        0xA4050100
 144#define PBCR        0xA4050102
 145#define PCCR        0xA4050104
 146#define PDCR        0xA4050106
 147#define PECR        0xA4050108
 148#define PFCR        0xA405010A
 149#define PGCR        0xA405010C
 150#define PHCR        0xA405010E
 151#define PJCR        0xA4050110
 152#define PKCR        0xA4050112
 153#define PLCR        0xA4050114
 154#define PMCR        0xA4050116
 155#define PNCR        0xA4050118
 156#define PQCR        0xA405011A
 157#define PRCR        0xA405011C
 158#define PSCR        0xA405011E
 159#define PTCR        0xA4050140
 160#define PUCR        0xA4050142
 161#define PVCR        0xA4050144
 162#define PWCR        0xA4050146
 163#define PXCR        0xA4050148
 164#define PYCR        0xA405014A
 165#define PZCR        0xA405014C
 166#define PSELA       0xA405014E
 167#define PSELB       0xA4050150
 168#define PSELC       0xA4050152
 169#define PSELD       0xA4050154
 170#define PSELE       0xA4050156
 171#define HIZCRA      0xA4050158
 172#define HIZCRB      0xA405015A
 173#define HIZCRC      0xA405015C
 174#define HIZCRD      0xA405015E
 175#define MSELCRA     0xA4050180
 176#define MSELCRB     0xA4050182
 177#define PULCR       0xA4050184
 178#define DRVCRA      0xA405018A
 179#define DRVCRB      0xA405018C
 180
 181/* I/O Port */
 182#define PADR        0xA4050120
 183#define PBDR        0xA4050122
 184#define PCDR        0xA4050124
 185#define PDDR        0xA4050126
 186#define PEDR        0xA4050128
 187#define PFDR        0xA405012A
 188#define PGDR        0xA405012C
 189#define PHDR        0xA405012E
 190#define PJDR        0xA4050130
 191#define PKDR        0xA4050132
 192#define PLDR        0xA4050134
 193#define PMDR        0xA4050136
 194#define PNDR        0xA4050138
 195#define PQDR        0xA405013A
 196#define PRDR        0xA405013C
 197#define PSDR        0xA405013E
 198#define PTDR        0xA4050160
 199#define PUDR        0xA4050162
 200#define PVDR        0xA4050164
 201#define PWDR        0xA4050166
 202#define PXDR        0xA4050168
 203#define PYDR        0xA405016A
 204#define PZDR        0xA405016C
 205
 206/* Ether */
 207#define EDMR            0xA4600000
 208
 209/* UBC */
 210/* H-UDI */
 211
 212#endif /* _ASM_CPU_SH7724_H_ */
 213