1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#include <common.h>
16#include <errno.h>
17#include <spl.h>
18#include <asm/arch/cpu.h>
19#include <asm/arch/hardware.h>
20#include <asm/arch/omap.h>
21#include <asm/arch/ddr_defs.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/gpio.h>
24#include <asm/arch/mmc_host_def.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/arch/mem.h>
27#include <asm/io.h>
28#include <asm/emif.h>
29#include <asm/gpio.h>
30#include <i2c.h>
31#include <miiphy.h>
32#include <cpsw.h>
33#include <watchdog.h>
34#include "board.h"
35#include "../common/factoryset.h"
36#include <nand.h>
37
38#ifdef CONFIG_SPL_BUILD
39static struct draco_baseboard_id __attribute__((section(".data"))) settings;
40
41#if DDR_PLL_FREQ == 303
42#if !defined(CONFIG_TARGET_ETAMIN)
43
44const struct ddr3_data ddr3_default = {
45 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
46 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
47 0x0000093B, 0x0000014A,
48 "default name @303MHz \0",
49 "default marking \0",
50};
51#else
52
53const struct ddr3_data ddr3_default = {
54 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
55 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
56 0x0000093B, 0x0000018A,
57 "test-etamin \0",
58 "generic-8Gbit \0",
59};
60#endif
61#elif DDR_PLL_FREQ == 400
62
63const struct ddr3_data ddr3_default = {
64 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
65 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
66 0x00000618, 0x0000014A,
67 "default name @400MHz \0",
68 "default marking \0",
69};
70#endif
71
72static void set_default_ddr3_timings(void)
73{
74 printf("Set default DDR3 settings\n");
75 settings.ddr3 = ddr3_default;
76}
77
78static void print_ddr3_timings(void)
79{
80 printf("\nDDR3\n");
81 printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
82 printf("device:\t\t%s\n", settings.ddr3.manu_name);
83 printf("marking:\t%s\n", settings.ddr3.manu_marking);
84 printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
85 "default", "diff");
86 PRINTARGS(magic);
87 PRINTARGS(version);
88 PRINTARGS(ddr3_sratio);
89 PRINTARGS(iclkout);
90
91 PRINTARGS(dt0rdsratio0);
92 PRINTARGS(dt0wdsratio0);
93 PRINTARGS(dt0fwsratio0);
94 PRINTARGS(dt0wrsratio0);
95
96 PRINTARGS(sdram_tim1);
97 PRINTARGS(sdram_tim2);
98 PRINTARGS(sdram_tim3);
99
100 PRINTARGS(emif_ddr_phy_ctlr_1);
101
102 PRINTARGS(sdram_config);
103 PRINTARGS(ref_ctrl);
104 PRINTARGS(ioctr_val);
105}
106
107static void print_chip_data(void)
108{
109 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
110 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
111 printf("\nCPU BOARD\n");
112 printf("device: \t'%s'\n", settings.chip.sdevname);
113 printf("hw version: \t'%s'\n", settings.chip.shwver);
114 printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
115}
116#endif
117
118#define AM335X_NAND_ECC_MASK 0x0f
119#define AM335X_NAND_ECC_TYPE_16 0x02
120
121static int ecc_type;
122
123struct am335x_nand_geometry {
124 u32 magic;
125 u8 nand_geo_addr;
126 u8 nand_geo_page;
127 u8 nand_bus;
128};
129
130static int draco_read_nand_geometry(void)
131{
132 struct am335x_nand_geometry geo;
133
134
135 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
136 (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
137 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
138 return -EIO;
139 }
140 if (geo.magic != 0xa657b310) {
141 printf("%s: bad magic: %x\n", __func__, geo.magic);
142 return -EFAULT;
143 }
144 if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
145 ecc_type = 16;
146 else
147 ecc_type = 8;
148
149 return 0;
150}
151
152
153
154
155static int read_eeprom(void)
156{
157
158 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
159 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
160 return 1;
161 }
162
163#ifdef CONFIG_SPL_BUILD
164
165 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
166 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
167 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
168 set_default_ddr3_timings();
169 }
170
171 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
172 (uchar *)&settings.chip, sizeof(settings.chip)))
173 printf("Could not read chip settings\n");
174
175 if (ddr3_default.magic == settings.ddr3.magic &&
176 ddr3_default.version == settings.ddr3.version) {
177 printf("Using DDR3 settings from EEPROM\n");
178 } else {
179 if (ddr3_default.magic != settings.ddr3.magic)
180 printf("Warning: No valid DDR3 data in eeprom.\n");
181 if (ddr3_default.version != settings.ddr3.version)
182 printf("Warning: DDR3 data version does not match.\n");
183
184 printf("Using default settings\n");
185 set_default_ddr3_timings();
186 }
187
188 if (MAGIC_CHIP == settings.chip.magic)
189 print_chip_data();
190 else
191 printf("Warning: No chip data in eeprom\n");
192
193 print_ddr3_timings();
194
195 return draco_read_nand_geometry();
196#endif
197 return 0;
198}
199
200#ifdef CONFIG_SPL_BUILD
201static void board_init_ddr(void)
202{
203struct emif_regs draco_ddr3_emif_reg_data = {
204 .zq_config = 0x50074BE4,
205};
206
207struct ddr_data draco_ddr3_data = {
208};
209
210struct cmd_control draco_ddr3_cmd_ctrl_data = {
211};
212
213struct ctrl_ioregs draco_ddr3_ioregs = {
214};
215
216
217 draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
218 draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
219 draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
220 draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
221 settings.ddr3.emif_ddr_phy_ctlr_1;
222 draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
223 draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
224 draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
225
226 draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
227 draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
228 draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
229 draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
230
231 draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
232 draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
233 draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
234 draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
235 draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
236 draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
237
238 draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
239 draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
240 draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
241 draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
242 draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
243
244 config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
245 &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
246}
247
248static void spl_siemens_board_init(void)
249{
250 return;
251}
252#endif
253
254#ifdef CONFIG_BOARD_LATE_INIT
255int board_late_init(void)
256{
257 int ret;
258
259 ret = draco_read_nand_geometry();
260 if (ret != 0)
261 return ret;
262
263 nand_curr_device = 0;
264 omap_nand_switch_ecc(1, ecc_type);
265#ifdef CONFIG_TARGET_ETAMIN
266 nand_curr_device = 1;
267 omap_nand_switch_ecc(1, ecc_type);
268#endif
269#ifdef CONFIG_FACTORYSET
270
271 if (factory_dat.asn[0] != 0) {
272 env_set("dtb_name", (char *)factory_dat.asn);
273 } else {
274
275 env_set("dtb_name", "am335x-draco");
276 }
277#else
278 env_set("dtb_name", "am335x-draco");
279#endif
280
281 return 0;
282}
283#endif
284
285#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
286 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
287static void cpsw_control(int enabled)
288{
289
290
291 return;
292}
293
294static struct cpsw_slave_data cpsw_slaves[] = {
295 {
296 .slave_reg_ofs = 0x208,
297 .sliver_reg_ofs = 0xd80,
298 .phy_addr = 0,
299 .phy_if = PHY_INTERFACE_MODE_MII,
300 },
301};
302
303static struct cpsw_platform_data cpsw_data = {
304 .mdio_base = CPSW_MDIO_BASE,
305 .cpsw_base = CPSW_BASE,
306 .mdio_div = 0xff,
307 .channels = 4,
308 .cpdma_reg_ofs = 0x800,
309 .slaves = 1,
310 .slave_data = cpsw_slaves,
311 .ale_reg_ofs = 0xd00,
312 .ale_entries = 1024,
313 .host_port_reg_ofs = 0x108,
314 .hw_stats_reg_ofs = 0x900,
315 .bd_ram_ofs = 0x2000,
316 .mac_control = (1 << 5),
317 .control = cpsw_control,
318 .host_port_num = 0,
319 .version = CPSW_CTRL_VERSION_2,
320};
321
322#if defined(CONFIG_DRIVER_TI_CPSW) || \
323 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
324int board_eth_init(bd_t *bis)
325{
326 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
327 int n = 0;
328 int rv;
329
330 factoryset_env_set();
331
332
333 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
334
335 rv = cpsw_register(&cpsw_data);
336 if (rv < 0)
337 printf("Error %d registering CPSW switch\n", rv);
338 else
339 n += rv;
340 return n;
341}
342
343static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
344 char *const argv[])
345{
346
347 gpio_request(GPIO_LAN9303_NRST, "nRST");
348 gpio_direction_output(GPIO_LAN9303_NRST, 0);
349
350 udelay(200);
351 gpio_set_value(GPIO_LAN9303_NRST, 1);
352
353 return 0;
354};
355
356U_BOOT_CMD(
357 switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
358 "Reset LAN9303 switch via its reset pin",
359 ""
360);
361#endif
362#endif
363
364#ifdef CONFIG_NAND_CS_INIT
365
366static const u32 gpmc_nand_config[] = {
367 ETAMIN_NAND_GPMC_CONFIG1,
368 ETAMIN_NAND_GPMC_CONFIG2,
369 ETAMIN_NAND_GPMC_CONFIG3,
370 ETAMIN_NAND_GPMC_CONFIG4,
371 ETAMIN_NAND_GPMC_CONFIG5,
372 ETAMIN_NAND_GPMC_CONFIG6,
373
374};
375
376static void board_nand_cs_init(void)
377{
378 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
379 0x18000000, GPMC_SIZE_16M);
380}
381#endif
382
383#include "../common/board.c"
384
