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7#define COMMAND_0 0x00
8#define CMD_GO (1 << 31)
9#define CMD_CLE (1 << 30)
10#define CMD_ALE (1 << 29)
11#define CMD_PIO (1 << 28)
12#define CMD_TX (1 << 27)
13#define CMD_RX (1 << 26)
14#define CMD_SEC_CMD (1 << 25)
15#define CMD_AFT_DAT_MASK (1 << 24)
16#define CMD_AFT_DAT_DISABLE 0
17#define CMD_AFT_DAT_ENABLE (1 << 24)
18#define CMD_TRANS_SIZE_SHIFT 20
19#define CMD_TRANS_SIZE_PAGE 8
20#define CMD_A_VALID (1 << 19)
21#define CMD_B_VALID (1 << 18)
22#define CMD_RD_STATUS_CHK (1 << 17)
23#define CMD_R_BSY_CHK (1 << 16)
24#define CMD_CE7 (1 << 15)
25#define CMD_CE6 (1 << 14)
26#define CMD_CE5 (1 << 13)
27#define CMD_CE4 (1 << 12)
28#define CMD_CE3 (1 << 11)
29#define CMD_CE2 (1 << 10)
30#define CMD_CE1 (1 << 9)
31#define CMD_CE0 (1 << 8)
32#define CMD_CLE_BYTE_SIZE_SHIFT 4
33enum {
34 CMD_CLE_BYTES1 = 0,
35 CMD_CLE_BYTES2,
36 CMD_CLE_BYTES3,
37 CMD_CLE_BYTES4,
38};
39#define CMD_ALE_BYTE_SIZE_SHIFT 0
40enum {
41 CMD_ALE_BYTES1 = 0,
42 CMD_ALE_BYTES2,
43 CMD_ALE_BYTES3,
44 CMD_ALE_BYTES4,
45 CMD_ALE_BYTES5,
46 CMD_ALE_BYTES6,
47 CMD_ALE_BYTES7,
48 CMD_ALE_BYTES8
49};
50
51#define STATUS_0 0x04
52#define STATUS_RBSY0 (1 << 8)
53
54#define ISR_0 0x08
55#define ISR_IS_CMD_DONE (1 << 5)
56#define ISR_IS_ECC_ERR (1 << 4)
57
58#define IER_0 0x0C
59
60#define CFG_0 0x10
61#define CFG_HW_ECC_MASK (1 << 31)
62#define CFG_HW_ECC_DISABLE 0
63#define CFG_HW_ECC_ENABLE (1 << 31)
64#define CFG_HW_ECC_SEL_MASK (1 << 30)
65#define CFG_HW_ECC_SEL_HAMMING 0
66#define CFG_HW_ECC_SEL_RS (1 << 30)
67#define CFG_HW_ECC_CORRECTION_MASK (1 << 29)
68#define CFG_HW_ECC_CORRECTION_DISABLE 0
69#define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29)
70#define CFG_PIPELINE_EN_MASK (1 << 28)
71#define CFG_PIPELINE_EN_DISABLE 0
72#define CFG_PIPELINE_EN_ENABLE (1 << 28)
73#define CFG_ECC_EN_TAG_MASK (1 << 27)
74#define CFG_ECC_EN_TAG_DISABLE 0
75#define CFG_ECC_EN_TAG_ENABLE (1 << 27)
76#define CFG_TVALUE_MASK (3 << 24)
77enum {
78 CFG_TVAL4 = 0 << 24,
79 CFG_TVAL6 = 1 << 24,
80 CFG_TVAL8 = 2 << 24
81};
82#define CFG_SKIP_SPARE_MASK (1 << 23)
83#define CFG_SKIP_SPARE_DISABLE 0
84#define CFG_SKIP_SPARE_ENABLE (1 << 23)
85#define CFG_COM_BSY_MASK (1 << 22)
86#define CFG_COM_BSY_DISABLE 0
87#define CFG_COM_BSY_ENABLE (1 << 22)
88#define CFG_BUS_WIDTH_MASK (1 << 21)
89#define CFG_BUS_WIDTH_8BIT 0
90#define CFG_BUS_WIDTH_16BIT (1 << 21)
91#define CFG_LPDDR1_MODE_MASK (1 << 20)
92#define CFG_LPDDR1_MODE_DISABLE 0
93#define CFG_LPDDR1_MODE_ENABLE (1 << 20)
94#define CFG_EDO_MODE_MASK (1 << 19)
95#define CFG_EDO_MODE_DISABLE 0
96#define CFG_EDO_MODE_ENABLE (1 << 19)
97#define CFG_PAGE_SIZE_SEL_MASK (7 << 16)
98enum {
99 CFG_PAGE_SIZE_256 = 0 << 16,
100 CFG_PAGE_SIZE_512 = 1 << 16,
101 CFG_PAGE_SIZE_1024 = 2 << 16,
102 CFG_PAGE_SIZE_2048 = 3 << 16,
103 CFG_PAGE_SIZE_4096 = 4 << 16
104};
105#define CFG_SKIP_SPARE_SEL_MASK (3 << 14)
106enum {
107 CFG_SKIP_SPARE_SEL_4 = 0 << 14,
108 CFG_SKIP_SPARE_SEL_8 = 1 << 14,
109 CFG_SKIP_SPARE_SEL_12 = 2 << 14,
110 CFG_SKIP_SPARE_SEL_16 = 3 << 14
111};
112#define CFG_TAG_BYTE_SIZE_MASK 0x1FF
113
114#define TIMING_0 0x14
115#define TIMING_TRP_RESP_CNT_SHIFT 28
116#define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT)
117#define TIMING_TWB_CNT_SHIFT 24
118#define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT)
119#define TIMING_TCR_TAR_TRR_CNT_SHIFT 20
120#define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT)
121#define TIMING_TWHR_CNT_SHIFT 16
122#define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT)
123#define TIMING_TCS_CNT_SHIFT 14
124#define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT)
125#define TIMING_TWH_CNT_SHIFT 12
126#define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT)
127#define TIMING_TWP_CNT_SHIFT 8
128#define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT)
129#define TIMING_TRH_CNT_SHIFT 4
130#define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT)
131#define TIMING_TRP_CNT_SHIFT 0
132#define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT)
133
134#define RESP_0 0x18
135
136#define TIMING2_0 0x1C
137#define TIMING2_TADL_CNT_SHIFT 0
138#define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT)
139
140#define CMD_REG1_0 0x20
141#define CMD_REG2_0 0x24
142#define ADDR_REG1_0 0x28
143#define ADDR_REG2_0 0x2C
144
145#define DMA_MST_CTRL_0 0x30
146#define DMA_MST_CTRL_GO_MASK (1 << 31)
147#define DMA_MST_CTRL_GO_DISABLE 0
148#define DMA_MST_CTRL_GO_ENABLE (1 << 31)
149#define DMA_MST_CTRL_DIR_MASK (1 << 30)
150#define DMA_MST_CTRL_DIR_READ 0
151#define DMA_MST_CTRL_DIR_WRITE (1 << 30)
152#define DMA_MST_CTRL_PERF_EN_MASK (1 << 29)
153#define DMA_MST_CTRL_PERF_EN_DISABLE 0
154#define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29)
155#define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27)
156#define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0
157#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27)
158#define DMA_MST_CTRL_BURST_SIZE_SHIFT 24
159#define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT)
160enum {
161 DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
162 DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
163 DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
164 DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT
165};
166#define DMA_MST_CTRL_IS_DMA_DONE (1 << 20)
167#define DMA_MST_CTRL_EN_A_MASK (1 << 2)
168#define DMA_MST_CTRL_EN_A_DISABLE 0
169#define DMA_MST_CTRL_EN_A_ENABLE (1 << 2)
170#define DMA_MST_CTRL_EN_B_MASK (1 << 1)
171#define DMA_MST_CTRL_EN_B_DISABLE 0
172#define DMA_MST_CTRL_EN_B_ENABLE (1 << 1)
173
174#define DMA_CFG_A_0 0x34
175#define DMA_CFG_B_0 0x38
176#define FIFO_CTRL_0 0x3C
177#define DATA_BLOCK_PTR_0 0x40
178#define TAG_PTR_0 0x44
179#define ECC_PTR_0 0x48
180
181#define DEC_STATUS_0 0x4C
182#define DEC_STATUS_A_ECC_FAIL (1 << 1)
183#define DEC_STATUS_B_ECC_FAIL (1 << 0)
184
185#define BCH_CONFIG_0 0xCC
186#define BCH_CONFIG_BCH_TVALUE_SHIFT 4
187#define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT)
188enum {
189 BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT,
190 BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT,
191 BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT,
192 BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT
193};
194#define BCH_CONFIG_BCH_ECC_MASK (1 << 0)
195#define BCH_CONFIG_BCH_ECC_DISABLE 0
196#define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0)
197
198#define BCH_DEC_RESULT_0 0xD0
199#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8)
200#define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF
201
202#define BCH_DEC_STATUS_BUF_0 0xD4
203#define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000
204#define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000
205#define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14)
206#define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13)
207#define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8)
208#define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF
209
210#define LP_OPTIONS 0
211
212struct nand_ctlr {
213 u32 command;
214 u32 status;
215 u32 isr;
216 u32 ier;
217 u32 config;
218 u32 timing;
219 u32 resp;
220 u32 timing2;
221 u32 cmd_reg1;
222 u32 cmd_reg2;
223 u32 addr_reg1;
224 u32 addr_reg2;
225 u32 dma_mst_ctrl;
226 u32 dma_cfg_a;
227 u32 dma_cfg_b;
228 u32 fifo_ctrl;
229 u32 data_block_ptr;
230 u32 tag_ptr;
231 u32 resv1;
232 u32 dec_status;
233 u32 hwstatus_cmd;
234 u32 hwstatus_mask;
235 u32 resv2[29];
236 u32 bch_config;
237 u32 bch_dec_result;
238 u32 bch_dec_status_buf;
239
240};
241
