1/* SPDX-License-Identifier: GPL-2.0+ */ 2#ifndef CS8900_H 3#define CS8900_H 4/* 5 * Cirrus Logic CS8900A Ethernet 6 * 7 * (C) 2009 Ben Warren , biggerbadderben@gmail.com 8 * Converted to use CONFIG_NET_MULTI API 9 * 10 * (C) Copyright 2002 11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 12 * Marius Groeger <mgroeger@sysgo.de> 13 * 14 * Copyright (C) 1999 Ben Williamson <benw@pobox.com> 15 * 16 * This program is loaded into SRAM in bootstrap mode, where it waits 17 * for commands on UART1 to read and write memory, jump to code etc. 18 * A design goal for this program is to be entirely independent of the 19 * target board. Anything with a CL-PS7111 or EP7211 should be able to run 20 * this code in bootstrap mode. All the board specifics can be handled on 21 * the host. 22 */ 23 24#include <asm/types.h> 25#include <config.h> 26 27#define CS8900_DRIVERNAME "CS8900" 28/* although the registers are 16 bit, they are 32-bit aligned on the 29 EDB7111. so we have to read them as 32-bit registers and ignore the 30 upper 16-bits. i'm not sure if this holds for the EDB7211. */ 31 32#ifdef CONFIG_CS8900_BUS16 33 /* 16 bit aligned registers, 16 bit wide */ 34 #define CS8900_REG u16 35#elif defined(CONFIG_CS8900_BUS32) 36 /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ 37 #define CS8900_REG u32 38#else 39 #error unknown bussize ... 40#endif 41 42struct cs8900_regs { 43 CS8900_REG rtdata; 44 CS8900_REG pad0; 45 CS8900_REG txcmd; 46 CS8900_REG txlen; 47 CS8900_REG isq; 48 CS8900_REG pptr; 49 CS8900_REG pdata; 50}; 51 52struct cs8900_priv { 53 struct cs8900_regs *regs; 54}; 55 56#define ISQ_RxEvent 0x04 57#define ISQ_TxEvent 0x08 58#define ISQ_BufEvent 0x0C 59#define ISQ_RxMissEvent 0x10 60#define ISQ_TxColEvent 0x12 61#define ISQ_EventMask 0x3F 62 63/* packet page register offsets */ 64 65/* bus interface registers */ 66#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ 67#define PP_ChipRev 0x0002 /* Chip revision, model codes */ 68 69#define PP_IntReg 0x0022 /* Interrupt configuration */ 70#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ 71#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ 72#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ 73#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ 74 75/* status and control registers */ 76 77#define PP_RxCFG 0x0102 /* Receiver configuration */ 78#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ 79#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ 80#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ 81#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ 82#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ 83#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ 84#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ 85#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ 86#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ 87 88#define PP_RxCTL 0x0104 /* Receiver control */ 89#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ 90#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ 91#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ 92#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ 93#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ 94#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ 95#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ 96#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ 97#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ 98 99#define PP_TxCFG 0x0106 /* Transmit configuration */ 100#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ 101#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ 102#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ 103#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ 104#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ 105#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ 106#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ 107 108#define PP_TxCmd 0x0108 /* Transmit command status */ 109#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ 110#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ 111#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ 112#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ 113#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ 114#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ 115#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ 116#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ 117 118#define PP_BufCFG 0x010A /* Buffer configuration */ 119#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ 120#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ 121#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ 122#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ 123#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ 124#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ 125#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ 126#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ 127#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ 128 129#define PP_LineCTL 0x0112 /* Line control */ 130#define PP_LineCTL_Rx 0x0040 /* Enable receiver */ 131#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ 132#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ 133#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ 134#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ 135#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ 136#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ 137#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ 138 139#define PP_SelfCTL 0x0114 /* Chip self control */ 140#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ 141#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ 142#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ 143#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ 144#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ 145#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ 146#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ 147#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ 148 149#define PP_BusCTL 0x0116 /* Bus control */ 150#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ 151#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ 152#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ 153#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ 154#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ 155#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ 156#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ 157#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ 158 159#define PP_TestCTL 0x0118 /* Test control */ 160#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ 161#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ 162#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ 163#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ 164#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ 165 166#define PP_ISQ 0x0120 /* Interrupt Status Queue */ 167 168#define PP_RER 0x0124 /* Receive event */ 169#define PP_RER_IAHash 0x0040 /* Frame hash match */ 170#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ 171#define PP_RER_RxOK 0x0100 /* Frame received with no errors */ 172#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ 173#define PP_RER_IA 0x0400 /* Frame address matched IA */ 174#define PP_RER_Broadcast 0x0800 /* Broadcast frame */ 175#define PP_RER_CRC 0x1000 /* Frame had CRC error */ 176#define PP_RER_RUNT 0x2000 /* Runt frame */ 177#define PP_RER_EXTRA 0x4000 /* Frame was too long */ 178 179#define PP_TER 0x0128 /* Transmit event */ 180#define PP_TER_CRS 0x0040 /* Carrier lost */ 181#define PP_TER_SQE 0x0080 /* Signal Quality Error */ 182#define PP_TER_TxOK 0x0100 /* Packet sent without error */ 183#define PP_TER_Late 0x0200 /* Out of window */ 184#define PP_TER_Jabber 0x0400 /* Stuck transmit? */ 185#define PP_TER_NumCollisions 0x7800 /* Number of collisions */ 186#define PP_TER_16Collisions 0x8000 /* > 16 collisions */ 187 188#define PP_BER 0x012C /* Buffer event */ 189#define PP_BER_SWint 0x0040 /* Software interrupt */ 190#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ 191#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ 192#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ 193#define PP_BER_RxMiss 0x0400 /* Received frame missed */ 194#define PP_BER_Rx128 0x0800 /* 128 bytes received */ 195#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ 196 197#define PP_RxMiss 0x0130 /* Receiver miss counter */ 198 199#define PP_TxCol 0x0132 /* Transmit collision counter */ 200 201#define PP_LineSTAT 0x0134 /* Line status */ 202#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ 203#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ 204#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ 205#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ 206#define PP_LineSTAT_CRS 0x4000 /* Frame being received */ 207 208#define PP_SelfSTAT 0x0136 /* Chip self status */ 209#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ 210#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ 211#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ 212#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ 213#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ 214#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ 215#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ 216 217#define PP_BusSTAT 0x0138 /* Bus status */ 218#define PP_BusSTAT_TxBid 0x0080 /* Tx error */ 219#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ 220 221#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ 222 223/* initiate transmit registers */ 224 225#define PP_TxCommand 0x0144 /* Tx Command */ 226#define PP_TxLength 0x0146 /* Tx Length */ 227 228 229/* address filter registers */ 230 231#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ 232#define PP_IA 0x0158 /* Individual address (MAC) */ 233 234/* EEPROM Kram */ 235#define SI_BUSY 0x0100 236#define PP_EECMD 0x0040 /* NVR Interface Command register */ 237#define PP_EEData 0x0042 /* NVR Interface Data Register */ 238#define EEPROM_WRITE_EN 0x00F0 239#define EEPROM_WRITE_DIS 0x0000 240#define EEPROM_WRITE_CMD 0x0100 241#define EEPROM_READ_CMD 0x0200 242#define EEPROM_ERASE_CMD 0x0300 243 244/* Exported functions */ 245int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *); 246int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort); 247 248#endif /* CS8900_H */ 249