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10#include <common.h>
11#include <clk.h>
12#include <dm.h>
13#include <errno.h>
14#include <malloc.h>
15#include <reset.h>
16#include <spi.h>
17#include <spi_flash.h>
18#include <asm/io.h>
19#include <asm/arch/stm32.h>
20#include <linux/ioport.h>
21
22struct stm32_qspi_regs {
23 u32 cr;
24 u32 dcr;
25 u32 sr;
26 u32 fcr;
27 u32 dlr;
28 u32 ccr;
29 u32 ar;
30 u32 abr;
31 u32 dr;
32 u32 psmkr;
33 u32 psmar;
34 u32 pir;
35 u32 lptr;
36};
37
38
39
40
41#define STM32_QSPI_CR_EN BIT(0)
42#define STM32_QSPI_CR_ABORT BIT(1)
43#define STM32_QSPI_CR_DMAEN BIT(2)
44#define STM32_QSPI_CR_TCEN BIT(3)
45#define STM32_QSPI_CR_SSHIFT BIT(4)
46#define STM32_QSPI_CR_DFM BIT(6)
47#define STM32_QSPI_CR_FSEL BIT(7)
48#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
49#define STM32_QSPI_CR_FTHRES_SHIFT (8)
50#define STM32_QSPI_CR_TEIE BIT(16)
51#define STM32_QSPI_CR_TCIE BIT(17)
52#define STM32_QSPI_CR_FTIE BIT(18)
53#define STM32_QSPI_CR_SMIE BIT(19)
54#define STM32_QSPI_CR_TOIE BIT(20)
55#define STM32_QSPI_CR_APMS BIT(22)
56#define STM32_QSPI_CR_PMM BIT(23)
57#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
58#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
59
60
61
62
63#define STM32_QSPI_DCR_CKMODE BIT(0)
64#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
65#define STM32_QSPI_DCR_CSHT_SHIFT (8)
66#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
67#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
68
69
70
71
72#define STM32_QSPI_SR_TEF BIT(0)
73#define STM32_QSPI_SR_TCF BIT(1)
74#define STM32_QSPI_SR_FTF BIT(2)
75#define STM32_QSPI_SR_SMF BIT(3)
76#define STM32_QSPI_SR_TOF BIT(4)
77#define STM32_QSPI_SR_BUSY BIT(5)
78#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
79#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
80
81
82
83
84#define STM32_QSPI_FCR_CTEF BIT(0)
85#define STM32_QSPI_FCR_CTCF BIT(1)
86#define STM32_QSPI_FCR_CSMF BIT(3)
87#define STM32_QSPI_FCR_CTOF BIT(4)
88
89
90
91
92#define STM32_QSPI_CCR_DDRM BIT(31)
93#define STM32_QSPI_CCR_DHHC BIT(30)
94#define STM32_QSPI_CCR_SIOO BIT(28)
95#define STM32_QSPI_CCR_FMODE_SHIFT (26)
96#define STM32_QSPI_CCR_DMODE_SHIFT (24)
97#define STM32_QSPI_CCR_DCYC_SHIFT (18)
98#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
99#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
100#define STM32_QSPI_CCR_ABMODE_SHIFT (14)
101#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
102#define STM32_QSPI_CCR_ADMODE_SHIFT (10)
103#define STM32_QSPI_CCR_IMODE_SHIFT (8)
104#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
105
106enum STM32_QSPI_CCR_IMODE {
107 STM32_QSPI_CCR_IMODE_NONE = 0,
108 STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
109 STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
110 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
111};
112
113enum STM32_QSPI_CCR_ADMODE {
114 STM32_QSPI_CCR_ADMODE_NONE = 0,
115 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
116 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
117 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
118};
119
120enum STM32_QSPI_CCR_ADSIZE {
121 STM32_QSPI_CCR_ADSIZE_8BIT = 0,
122 STM32_QSPI_CCR_ADSIZE_16BIT = 1,
123 STM32_QSPI_CCR_ADSIZE_24BIT = 2,
124 STM32_QSPI_CCR_ADSIZE_32BIT = 3,
125};
126
127enum STM32_QSPI_CCR_ABMODE {
128 STM32_QSPI_CCR_ABMODE_NONE = 0,
129 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
130 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
131 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
132};
133
134enum STM32_QSPI_CCR_ABSIZE {
135 STM32_QSPI_CCR_ABSIZE_8BIT = 0,
136 STM32_QSPI_CCR_ABSIZE_16BIT = 1,
137 STM32_QSPI_CCR_ABSIZE_24BIT = 2,
138 STM32_QSPI_CCR_ABSIZE_32BIT = 3,
139};
140
141enum STM32_QSPI_CCR_DMODE {
142 STM32_QSPI_CCR_DMODE_NONE = 0,
143 STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
144 STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
145 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
146};
147
148enum STM32_QSPI_CCR_FMODE {
149 STM32_QSPI_CCR_IND_WRITE = 0,
150 STM32_QSPI_CCR_IND_READ = 1,
151 STM32_QSPI_CCR_AUTO_POLL = 2,
152 STM32_QSPI_CCR_MEM_MAP = 3,
153};
154
155
156#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
157
158#define STM32_MAX_NORCHIP 2
159
160struct stm32_qspi_platdata {
161 u32 base;
162 u32 memory_map;
163 u32 max_hz;
164};
165
166struct stm32_qspi_priv {
167 struct stm32_qspi_regs *regs;
168 ulong clock_rate;
169 u32 max_hz;
170 u32 mode;
171
172 u32 command;
173 u32 address;
174 u32 dummycycles;
175#define CMD_HAS_ADR BIT(24)
176#define CMD_HAS_DUMMY BIT(25)
177#define CMD_HAS_DATA BIT(26)
178};
179
180static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181{
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183}
184
185static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186{
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188}
189
190static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191{
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
193 ;
194}
195
196static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197{
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
199 ;
200}
201
202static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203{
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
205 ;
206}
207
208static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209{
210 u32 fsize = fls(size) - 1;
211
212 clrsetbits_le32(&priv->regs->dcr,
213 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
214 fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215}
216
217static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
218{
219 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
220 cs ? STM32_QSPI_CR_FSEL : 0);
221}
222
223static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
224{
225 unsigned int ccr_reg = 0;
226 u8 imode, admode, dmode;
227 u32 mode = priv->mode;
228 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
229
230 imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
231 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
232
233 if (mode & SPI_RX_QUAD) {
234 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
235 if (mode & SPI_TX_QUAD) {
236 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
237 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
238 }
239 } else if (mode & SPI_RX_DUAL) {
240 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
241 if (mode & SPI_TX_DUAL) {
242 imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
243 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
244 }
245 } else {
246 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
247 }
248
249 if (priv->command & CMD_HAS_DATA)
250 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
251
252 if (priv->command & CMD_HAS_DUMMY)
253 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
254 << STM32_QSPI_CCR_DCYC_SHIFT);
255
256 if (priv->command & CMD_HAS_ADR) {
257 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
258 << STM32_QSPI_CCR_ADSIZE_SHIFT);
259 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
260 }
261 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
262 ccr_reg |= cmd;
263 return ccr_reg;
264}
265
266static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
267 struct spi_flash *flash)
268{
269 unsigned int ccr_reg;
270
271 priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
272 | CMD_HAS_DUMMY;
273 priv->dummycycles = flash->dummy_byte * 8;
274
275 ccr_reg = _stm32_qspi_gen_ccr(priv);
276 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
277
278 _stm32_qspi_wait_for_not_busy(priv);
279
280 writel(ccr_reg, &priv->regs->ccr);
281
282 priv->dummycycles = 0;
283}
284
285static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
286{
287 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
288}
289
290static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
291 u32 length)
292{
293 writel(length - 1, &priv->regs->dlr);
294}
295
296static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
297{
298 writel(cr_reg, &priv->regs->ccr);
299
300 if (priv->command & CMD_HAS_ADR)
301 writel(priv->address, &priv->regs->ar);
302}
303
304static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
305 struct spi_flash *flash, unsigned int bitlen,
306 const u8 *dout, u8 *din, unsigned long flags)
307{
308 unsigned int words = bitlen / 8;
309 u32 ccr_reg;
310 int i;
311
312 if (flags & SPI_XFER_MMAP) {
313 _stm32_qspi_enable_mmap(priv, flash);
314 return 0;
315 } else if (flags & SPI_XFER_MMAP_END) {
316 _stm32_qspi_disable_mmap(priv);
317 return 0;
318 }
319
320 if (bitlen == 0)
321 return -1;
322
323 if (bitlen % 8) {
324 debug("spi_xfer: Non byte aligned SPI transfer\n");
325 return -1;
326 }
327
328 if (dout && din) {
329 debug("spi_xfer: QSPI cannot have data in and data out set\n");
330 return -1;
331 }
332
333 if (!dout && (flags & SPI_XFER_BEGIN)) {
334 debug("spi_xfer: QSPI transfer must begin with command\n");
335 return -1;
336 }
337
338 if (dout) {
339 if (flags & SPI_XFER_BEGIN) {
340
341 priv->command = dout[0] | CMD_HAS_DATA;
342 if (words >= 4) {
343
344 priv->address = (dout[1] << 16) |
345 (dout[2] << 8) | dout[3];
346 priv->command |= CMD_HAS_ADR;
347 }
348
349 if (words > 4) {
350
351 priv->dummycycles = (words - 4) * 8;
352 priv->command |= CMD_HAS_DUMMY;
353 }
354
355 if (flags & SPI_XFER_END) {
356
357 priv->command &= ~(CMD_HAS_DATA);
358 }
359 }
360
361 if (flags & SPI_XFER_END) {
362 ccr_reg = _stm32_qspi_gen_ccr(priv);
363 ccr_reg |= STM32_QSPI_CCR_IND_WRITE
364 << STM32_QSPI_CCR_FMODE_SHIFT;
365
366 _stm32_qspi_wait_for_not_busy(priv);
367
368 if (priv->command & CMD_HAS_DATA)
369 _stm32_qspi_set_xfer_length(priv, words);
370
371 _stm32_qspi_start_xfer(priv, ccr_reg);
372
373 debug("%s: write: ccr:0x%08x adr:0x%08x\n",
374 __func__, priv->regs->ccr, priv->regs->ar);
375
376 if (priv->command & CMD_HAS_DATA) {
377 _stm32_qspi_wait_for_ftf(priv);
378
379 debug("%s: words:%d data:", __func__, words);
380
381 i = 0;
382 while (words > i) {
383 writeb(dout[i], &priv->regs->dr);
384 debug("%02x ", dout[i]);
385 i++;
386 }
387 debug("\n");
388
389 _stm32_qspi_wait_for_complete(priv);
390 } else {
391 _stm32_qspi_wait_for_not_busy(priv);
392 }
393 }
394 } else if (din) {
395 ccr_reg = _stm32_qspi_gen_ccr(priv);
396 ccr_reg |= STM32_QSPI_CCR_IND_READ
397 << STM32_QSPI_CCR_FMODE_SHIFT;
398
399 _stm32_qspi_wait_for_not_busy(priv);
400
401 _stm32_qspi_set_xfer_length(priv, words);
402
403 _stm32_qspi_start_xfer(priv, ccr_reg);
404
405 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
406 priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
407
408 debug("%s: data:", __func__);
409
410 i = 0;
411 while (words > i) {
412 din[i] = readb(&priv->regs->dr);
413 debug("%02x ", din[i]);
414 i++;
415 }
416 debug("\n");
417 }
418
419 return 0;
420}
421
422static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
423{
424 struct resource res_regs, res_mem;
425 struct stm32_qspi_platdata *plat = bus->platdata;
426 int ret;
427
428 ret = dev_read_resource_byname(bus, "qspi", &res_regs);
429 if (ret) {
430 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
431 return -ENOMEM;
432 }
433 ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
434 if (ret) {
435 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
436 return -ENOMEM;
437 }
438
439 plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
440 STM32_QSPI_DEFAULT_SCK_FREQ);
441
442 plat->base = res_regs.start;
443 plat->memory_map = res_mem.start;
444
445 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
446 __func__,
447 plat->base,
448 plat->memory_map,
449 plat->max_hz
450 );
451
452 return 0;
453}
454
455static int stm32_qspi_probe(struct udevice *bus)
456{
457 struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
458 struct stm32_qspi_priv *priv = dev_get_priv(bus);
459 struct dm_spi_bus *dm_spi_bus;
460 struct clk clk;
461 struct reset_ctl reset_ctl;
462 int ret;
463
464 dm_spi_bus = bus->uclass_priv;
465
466 dm_spi_bus->max_hz = plat->max_hz;
467
468 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
469
470 priv->max_hz = plat->max_hz;
471
472 ret = clk_get_by_index(bus, 0, &clk);
473 if (ret < 0)
474 return ret;
475
476 ret = clk_enable(&clk);
477
478 if (ret) {
479 dev_err(bus, "failed to enable clock\n");
480 return ret;
481 }
482
483 priv->clock_rate = clk_get_rate(&clk);
484 if (priv->clock_rate < 0) {
485 clk_disable(&clk);
486 return priv->clock_rate;
487 }
488
489 ret = reset_get_by_index(bus, 0, &reset_ctl);
490 if (ret) {
491 if (ret != -ENOENT) {
492 dev_err(bus, "failed to get reset\n");
493 clk_disable(&clk);
494 return ret;
495 }
496 } else {
497
498 reset_assert(&reset_ctl);
499 udelay(2);
500 reset_deassert(&reset_ctl);
501 }
502
503 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
504
505 return 0;
506}
507
508static int stm32_qspi_remove(struct udevice *bus)
509{
510 return 0;
511}
512
513static int stm32_qspi_claim_bus(struct udevice *dev)
514{
515 struct stm32_qspi_priv *priv;
516 struct udevice *bus;
517 struct spi_flash *flash;
518 struct dm_spi_slave_platdata *slave_plat;
519
520 bus = dev->parent;
521 priv = dev_get_priv(bus);
522 flash = dev_get_uclass_priv(dev);
523 slave_plat = dev_get_parent_platdata(dev);
524
525 if (slave_plat->cs >= STM32_MAX_NORCHIP)
526 return -ENODEV;
527
528 _stm32_qspi_set_cs(priv, slave_plat->cs);
529
530 _stm32_qspi_set_flash_size(priv, flash->size);
531
532 _stm32_qspi_enable(priv);
533
534 return 0;
535}
536
537static int stm32_qspi_release_bus(struct udevice *dev)
538{
539 struct stm32_qspi_priv *priv;
540 struct udevice *bus;
541
542 bus = dev->parent;
543 priv = dev_get_priv(bus);
544
545 _stm32_qspi_disable(priv);
546
547 return 0;
548}
549
550static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
551 const void *dout, void *din, unsigned long flags)
552{
553 struct stm32_qspi_priv *priv;
554 struct udevice *bus;
555 struct spi_flash *flash;
556
557 bus = dev->parent;
558 priv = dev_get_priv(bus);
559 flash = dev_get_uclass_priv(dev);
560
561 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
562 (u8 *)din, flags);
563}
564
565static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
566{
567 struct stm32_qspi_platdata *plat = bus->platdata;
568 struct stm32_qspi_priv *priv = dev_get_priv(bus);
569 u32 qspi_clk = priv->clock_rate;
570 u32 prescaler = 255;
571 u32 csht;
572
573 if (speed > plat->max_hz)
574 speed = plat->max_hz;
575
576 if (speed > 0) {
577 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
578 if (prescaler > 255)
579 prescaler = 255;
580 else if (prescaler < 0)
581 prescaler = 0;
582 }
583
584 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
585 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
586
587 _stm32_qspi_wait_for_not_busy(priv);
588
589 clrsetbits_le32(&priv->regs->cr,
590 STM32_QSPI_CR_PRESCALER_MASK <<
591 STM32_QSPI_CR_PRESCALER_SHIFT,
592 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
593
594 clrsetbits_le32(&priv->regs->dcr,
595 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
596 csht << STM32_QSPI_DCR_CSHT_SHIFT);
597
598 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
599 (qspi_clk / (prescaler + 1)));
600
601 return 0;
602}
603
604static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
605{
606 struct stm32_qspi_priv *priv = dev_get_priv(bus);
607
608 _stm32_qspi_wait_for_not_busy(priv);
609
610 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
611 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
612 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
613 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
614 else
615 return -ENODEV;
616
617 if (mode & SPI_CS_HIGH)
618 return -ENODEV;
619
620 if (mode & SPI_RX_QUAD)
621 priv->mode |= SPI_RX_QUAD;
622 else if (mode & SPI_RX_DUAL)
623 priv->mode |= SPI_RX_DUAL;
624 else
625 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
626
627 if (mode & SPI_TX_QUAD)
628 priv->mode |= SPI_TX_QUAD;
629 else if (mode & SPI_TX_DUAL)
630 priv->mode |= SPI_TX_DUAL;
631 else
632 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
633
634 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
635
636 if (mode & SPI_RX_QUAD)
637 debug("quad, tx: ");
638 else if (mode & SPI_RX_DUAL)
639 debug("dual, tx: ");
640 else
641 debug("single, tx: ");
642
643 if (mode & SPI_TX_QUAD)
644 debug("quad\n");
645 else if (mode & SPI_TX_DUAL)
646 debug("dual\n");
647 else
648 debug("single\n");
649
650 return 0;
651}
652
653static const struct dm_spi_ops stm32_qspi_ops = {
654 .claim_bus = stm32_qspi_claim_bus,
655 .release_bus = stm32_qspi_release_bus,
656 .xfer = stm32_qspi_xfer,
657 .set_speed = stm32_qspi_set_speed,
658 .set_mode = stm32_qspi_set_mode,
659};
660
661static const struct udevice_id stm32_qspi_ids[] = {
662 { .compatible = "st,stm32-qspi" },
663 { .compatible = "st,stm32f469-qspi" },
664 { }
665};
666
667U_BOOT_DRIVER(stm32_qspi) = {
668 .name = "stm32_qspi",
669 .id = UCLASS_SPI,
670 .of_match = stm32_qspi_ids,
671 .ops = &stm32_qspi_ops,
672 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
673 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
674 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
675 .probe = stm32_qspi_probe,
676 .remove = stm32_qspi_remove,
677};
678
