1
2
3
4
5
6
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/omap.h>
11#include <malloc.h>
12#include <spi.h>
13#include <dm.h>
14#include <asm/gpio.h>
15#include <asm/omap_gpio.h>
16#include <asm/omap_common.h>
17#include <asm/ti-common/ti-edma3.h>
18#include <linux/kernel.h>
19#include <regmap.h>
20#include <syscon.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24
25#define QSPI_TIMEOUT 2000000
26#define QSPI_FCLK 192000000
27#define QSPI_DRA7XX_FCLK 76800000
28#define QSPI_WLEN_MAX_BITS 128
29#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
30#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
31
32#define QSPI_CLK_EN BIT(31)
33#define QSPI_CLK_DIV_MAX 0xffff
34
35#define QSPI_EN_CS(n) (n << 28)
36#define QSPI_WLEN(n) ((n-1) << 19)
37#define QSPI_3_PIN BIT(18)
38#define QSPI_RD_SNGL BIT(16)
39#define QSPI_WR_SNGL (2 << 16)
40#define QSPI_INVAL (4 << 16)
41#define QSPI_RD_QUAD (7 << 16)
42
43#define QSPI_DD(m, n) (m << (3 + n*8))
44#define QSPI_CKPHA(n) (1 << (2 + n*8))
45#define QSPI_CSPOL(n) (1 << (1 + n*8))
46#define QSPI_CKPOL(n) (1 << (n*8))
47
48#define QSPI_WC BIT(1)
49#define QSPI_BUSY BIT(0)
50#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
51#define QSPI_XFER_DONE QSPI_WC
52#define MM_SWITCH 0x01
53#define MEM_CS(cs) ((cs + 1) << 8)
54#define MEM_CS_UNSELECT 0xfffff8ff
55#define MMAP_START_ADDR_DRA 0x5c000000
56#define MMAP_START_ADDR_AM43x 0x30000000
57#define CORE_CTRL_IO 0x4a002558
58
59#define QSPI_CMD_READ (0x3 << 0)
60#define QSPI_CMD_READ_DUAL (0x6b << 0)
61#define QSPI_CMD_READ_QUAD (0x6c << 0)
62#define QSPI_CMD_READ_FAST (0x0b << 0)
63#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
64#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
65#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
66#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
67#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
68#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
69#define QSPI_CMD_WRITE (0x12 << 16)
70#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
71
72
73struct ti_qspi_regs {
74 u32 pid;
75 u32 pad0[3];
76 u32 sysconfig;
77 u32 pad1[3];
78 u32 int_stat_raw;
79 u32 int_stat_en;
80 u32 int_en_set;
81 u32 int_en_ctlr;
82 u32 intc_eoi;
83 u32 pad2[3];
84 u32 clk_ctrl;
85 u32 dc;
86 u32 cmd;
87 u32 status;
88 u32 data;
89 u32 setup0;
90 u32 setup1;
91 u32 setup2;
92 u32 setup3;
93 u32 memswitch;
94 u32 data1;
95 u32 data2;
96 u32 data3;
97};
98
99
100struct ti_qspi_priv {
101#ifndef CONFIG_DM_SPI
102 struct spi_slave slave;
103#else
104 void *memory_map;
105 uint max_hz;
106 u32 num_cs;
107#endif
108 struct ti_qspi_regs *base;
109 void *ctrl_mod_mmap;
110 ulong fclk;
111 unsigned int mode;
112 u32 cmd;
113 u32 dc;
114};
115
116static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
117{
118 uint clk_div;
119
120 if (!hz)
121 clk_div = 0;
122 else
123 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
124
125
126 if (clk_div > QSPI_CLK_DIV_MAX)
127 clk_div = QSPI_CLK_DIV_MAX;
128
129 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
130
131
132 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
133 &priv->base->clk_ctrl);
134
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
136}
137
138static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
139{
140 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
141
142 readl(&priv->base->cmd);
143}
144
145static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
146{
147 priv->dc = 0;
148 if (mode & SPI_CPHA)
149 priv->dc |= QSPI_CKPHA(0);
150 if (mode & SPI_CPOL)
151 priv->dc |= QSPI_CKPOL(0);
152 if (mode & SPI_CS_HIGH)
153 priv->dc |= QSPI_CSPOL(0);
154
155 return 0;
156}
157
158static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
159{
160 writel(priv->dc, &priv->base->dc);
161 writel(0, &priv->base->cmd);
162 writel(0, &priv->base->data);
163
164 priv->dc <<= cs * 8;
165 writel(priv->dc, &priv->base->dc);
166
167 return 0;
168}
169
170static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
171{
172 writel(0, &priv->base->dc);
173 writel(0, &priv->base->cmd);
174 writel(0, &priv->base->data);
175}
176
177static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
178{
179 u32 val;
180
181 val = readl(ctrl_mod_mmap);
182 if (enable)
183 val |= MEM_CS(cs);
184 else
185 val &= MEM_CS_UNSELECT;
186 writel(val, ctrl_mod_mmap);
187}
188
189static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
190 const void *dout, void *din, unsigned long flags,
191 u32 cs)
192{
193 uint words = bitlen >> 3;
194 const uchar *txp = dout;
195 uchar *rxp = din;
196 uint status;
197 int timeout;
198
199
200 if (flags & SPI_XFER_MMAP) {
201 writel(MM_SWITCH, &priv->base->memswitch);
202 if (priv->ctrl_mod_mmap)
203 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
204 return 0;
205 } else if (flags & SPI_XFER_MMAP_END) {
206 writel(~MM_SWITCH, &priv->base->memswitch);
207 if (priv->ctrl_mod_mmap)
208 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
209 return 0;
210 }
211
212 if (bitlen == 0)
213 return -1;
214
215 if (bitlen % 8) {
216 debug("spi_xfer: Non byte aligned SPI transfer\n");
217 return -1;
218 }
219
220
221 priv->cmd = 0;
222 priv->cmd |= QSPI_WLEN(8);
223 priv->cmd |= QSPI_EN_CS(cs);
224 if (priv->mode & SPI_3WIRE)
225 priv->cmd |= QSPI_3_PIN;
226 priv->cmd |= 0xfff;
227
228 while (words) {
229 u8 xfer_len = 0;
230
231 if (txp) {
232 u32 cmd = priv->cmd;
233
234 if (words >= QSPI_WLEN_MAX_BYTES) {
235 u32 *txbuf = (u32 *)txp;
236 u32 data;
237
238 data = cpu_to_be32(*txbuf++);
239 writel(data, &priv->base->data3);
240 data = cpu_to_be32(*txbuf++);
241 writel(data, &priv->base->data2);
242 data = cpu_to_be32(*txbuf++);
243 writel(data, &priv->base->data1);
244 data = cpu_to_be32(*txbuf++);
245 writel(data, &priv->base->data);
246 cmd &= ~QSPI_WLEN_MASK;
247 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
248 xfer_len = QSPI_WLEN_MAX_BYTES;
249 } else {
250 writeb(*txp, &priv->base->data);
251 xfer_len = 1;
252 }
253 debug("tx cmd %08x dc %08x\n",
254 cmd | QSPI_WR_SNGL, priv->dc);
255 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
256 status = readl(&priv->base->status);
257 timeout = QSPI_TIMEOUT;
258 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
259 if (--timeout < 0) {
260 printf("spi_xfer: TX timeout!\n");
261 return -1;
262 }
263 status = readl(&priv->base->status);
264 }
265 txp += xfer_len;
266 debug("tx done, status %08x\n", status);
267 }
268 if (rxp) {
269 debug("rx cmd %08x dc %08x\n",
270 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
271 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
272 status = readl(&priv->base->status);
273 timeout = QSPI_TIMEOUT;
274 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
275 if (--timeout < 0) {
276 printf("spi_xfer: RX timeout!\n");
277 return -1;
278 }
279 status = readl(&priv->base->status);
280 }
281 *rxp++ = readl(&priv->base->data);
282 xfer_len = 1;
283 debug("rx done, status %08x, read %02x\n",
284 status, *(rxp-1));
285 }
286 words -= xfer_len;
287 }
288
289
290 if (flags & SPI_XFER_END)
291 ti_qspi_cs_deactivate(priv);
292
293 return 0;
294}
295
296
297#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
298void spi_flash_copy_mmap(void *data, void *offset, size_t len)
299{
300 unsigned int addr = (unsigned int) (data);
301 unsigned int edma_slot_num = 1;
302
303
304 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
305
306
307 enable_edma3_clocks();
308
309
310 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
311
312
313 disable_edma3_clocks();
314
315 *((unsigned int *)offset) += len;
316}
317#endif
318
319#ifndef CONFIG_DM_SPI
320
321static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
322{
323 return container_of(slave, struct ti_qspi_priv, slave);
324}
325
326int spi_cs_is_valid(unsigned int bus, unsigned int cs)
327{
328 return 1;
329}
330
331void spi_cs_activate(struct spi_slave *slave)
332{
333
334 return;
335}
336
337void spi_cs_deactivate(struct spi_slave *slave)
338{
339 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
340 ti_qspi_cs_deactivate(priv);
341}
342
343void spi_init(void)
344{
345
346}
347
348static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
349{
350 u32 memval = 0;
351
352#ifdef CONFIG_QSPI_QUAD_SUPPORT
353 struct spi_slave *slave = &priv->slave;
354 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
355 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
356 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
357 QSPI_NUM_DUMMY_BITS);
358 slave->mode |= SPI_RX_QUAD;
359#else
360 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
361 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
362 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
363 QSPI_NUM_DUMMY_BITS;
364#endif
365
366 writel(memval, &priv->base->setup0);
367}
368
369struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
370 unsigned int max_hz, unsigned int mode)
371{
372 struct ti_qspi_priv *priv;
373
374#ifdef CONFIG_AM43XX
375 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
376 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
377#endif
378
379 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
380 if (!priv) {
381 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
382 return NULL;
383 }
384
385 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
386 priv->mode = mode;
387#if defined(CONFIG_DRA7XX)
388 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
389 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
390 priv->fclk = QSPI_DRA7XX_FCLK;
391#else
392 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
393 priv->fclk = QSPI_FCLK;
394#endif
395
396 ti_spi_set_speed(priv, max_hz);
397
398#ifdef CONFIG_TI_SPI_MMAP
399 ti_spi_setup_spi_register(priv);
400#endif
401
402 return &priv->slave;
403}
404
405void spi_free_slave(struct spi_slave *slave)
406{
407 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
408 free(priv);
409}
410
411int spi_claim_bus(struct spi_slave *slave)
412{
413 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
414
415 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
416 __ti_qspi_set_mode(priv, priv->mode);
417 return __ti_qspi_claim_bus(priv, priv->slave.cs);
418}
419void spi_release_bus(struct spi_slave *slave)
420{
421 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
422
423 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
424 __ti_qspi_release_bus(priv);
425}
426
427int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
428 void *din, unsigned long flags)
429{
430 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
431
432 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
433 priv->slave.bus, priv->slave.cs, bitlen, flags);
434 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
435}
436
437#else
438
439static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
440 struct spi_slave *slave,
441 bool enable)
442{
443 u32 memval;
444 u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
445
446 if (!enable) {
447 writel(0, &priv->base->setup0);
448 return;
449 }
450
451 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
452
453 switch (mode) {
454 case SPI_RX_QUAD:
455 memval |= QSPI_CMD_READ_QUAD;
456 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
457 memval |= QSPI_SETUP0_READ_QUAD;
458 slave->mode |= SPI_RX_QUAD;
459 break;
460 case SPI_RX_DUAL:
461 memval |= QSPI_CMD_READ_DUAL;
462 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
463 memval |= QSPI_SETUP0_READ_DUAL;
464 break;
465 default:
466 memval |= QSPI_CMD_READ;
467 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
468 memval |= QSPI_SETUP0_READ_NORMAL;
469 break;
470 }
471
472 writel(memval, &priv->base->setup0);
473}
474
475
476static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
477{
478 struct ti_qspi_priv *priv = dev_get_priv(bus);
479
480 ti_spi_set_speed(priv, max_hz);
481
482 return 0;
483}
484
485static int ti_qspi_set_mode(struct udevice *bus, uint mode)
486{
487 struct ti_qspi_priv *priv = dev_get_priv(bus);
488 return __ti_qspi_set_mode(priv, mode);
489}
490
491static int ti_qspi_claim_bus(struct udevice *dev)
492{
493 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
494 struct spi_slave *slave = dev_get_parent_priv(dev);
495 struct ti_qspi_priv *priv;
496 struct udevice *bus;
497
498 bus = dev->parent;
499 priv = dev_get_priv(bus);
500
501 if (slave_plat->cs > priv->num_cs) {
502 debug("invalid qspi chip select\n");
503 return -EINVAL;
504 }
505
506 __ti_qspi_setup_memorymap(priv, slave, true);
507
508 return __ti_qspi_claim_bus(priv, slave_plat->cs);
509}
510
511static int ti_qspi_release_bus(struct udevice *dev)
512{
513 struct spi_slave *slave = dev_get_parent_priv(dev);
514 struct ti_qspi_priv *priv;
515 struct udevice *bus;
516
517 bus = dev->parent;
518 priv = dev_get_priv(bus);
519
520 __ti_qspi_setup_memorymap(priv, slave, false);
521 __ti_qspi_release_bus(priv);
522
523 return 0;
524}
525
526static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
527 const void *dout, void *din, unsigned long flags)
528{
529 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
530 struct ti_qspi_priv *priv;
531 struct udevice *bus;
532
533 bus = dev->parent;
534 priv = dev_get_priv(bus);
535
536 if (slave->cs > priv->num_cs) {
537 debug("invalid qspi chip select\n");
538 return -EINVAL;
539 }
540
541 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
542}
543
544static int ti_qspi_probe(struct udevice *bus)
545{
546 struct ti_qspi_priv *priv = dev_get_priv(bus);
547
548 priv->fclk = dev_get_driver_data(bus);
549
550 return 0;
551}
552
553static void *map_syscon_chipselects(struct udevice *bus)
554{
555#if CONFIG_IS_ENABLED(SYSCON)
556 struct udevice *syscon;
557 struct regmap *regmap;
558 const fdt32_t *cell;
559 int len, err;
560
561 err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
562 "syscon-chipselects", &syscon);
563 if (err) {
564 debug("%s: unable to find syscon device (%d)\n", __func__,
565 err);
566 return NULL;
567 }
568
569 regmap = syscon_get_regmap(syscon);
570 if (IS_ERR(regmap)) {
571 debug("%s: unable to find regmap (%ld)\n", __func__,
572 PTR_ERR(regmap));
573 return NULL;
574 }
575
576 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
577 "syscon-chipselects", &len);
578 if (len < 2*sizeof(fdt32_t)) {
579 debug("%s: offset not available\n", __func__);
580 return NULL;
581 }
582
583 return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
584#else
585 fdt_addr_t addr;
586 addr = devfdt_get_addr_index(bus, 2);
587 return (addr == FDT_ADDR_T_NONE) ? NULL :
588 map_physmem(addr, 0, MAP_NOCACHE);
589#endif
590}
591
592static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
593{
594 struct ti_qspi_priv *priv = dev_get_priv(bus);
595 const void *blob = gd->fdt_blob;
596 int node = dev_of_offset(bus);
597
598 priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
599 priv->base = map_physmem(devfdt_get_addr(bus),
600 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
601 priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
602 MAP_NOCACHE);
603
604 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
605 if (priv->max_hz < 0) {
606 debug("Error: Max frequency missing\n");
607 return -ENODEV;
608 }
609 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
610
611 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
612 (int)priv->base, priv->max_hz);
613
614 return 0;
615}
616
617static int ti_qspi_child_pre_probe(struct udevice *dev)
618{
619 struct spi_slave *slave = dev_get_parent_priv(dev);
620 struct udevice *bus = dev_get_parent(dev);
621 struct ti_qspi_priv *priv = dev_get_priv(bus);
622
623 slave->memory_map = priv->memory_map;
624 return 0;
625}
626
627static const struct dm_spi_ops ti_qspi_ops = {
628 .claim_bus = ti_qspi_claim_bus,
629 .release_bus = ti_qspi_release_bus,
630 .xfer = ti_qspi_xfer,
631 .set_speed = ti_qspi_set_speed,
632 .set_mode = ti_qspi_set_mode,
633};
634
635static const struct udevice_id ti_qspi_ids[] = {
636 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
637 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
638 { }
639};
640
641U_BOOT_DRIVER(ti_qspi) = {
642 .name = "ti_qspi",
643 .id = UCLASS_SPI,
644 .of_match = ti_qspi_ids,
645 .ops = &ti_qspi_ops,
646 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
647 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
648 .probe = ti_qspi_probe,
649 .child_pre_probe = ti_qspi_child_pre_probe,
650};
651#endif
652
