LXR uboot/drivers/spi/xilinx

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Xilinx SPI driver
   4 *
   5 * Supports 8 bit SPI transfers only, with or w/o FIFO
   6 *
   7 * Based on bfin_spi.c, by way of altera_spi.c
   8 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
   9 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
  10 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
  11 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
  12 * Copyright (c) 2005-2008 Analog Devices Inc.
  13 */
  14
  15#include <config.h>
  16#include <common.h>
  17#include <dm.h>
  18#include <errno.h>
  19#include <malloc.h>
  20#include <spi.h>
  21#include <asm/io.h>
  22
  23/*
  24 * [0]: http://www.xilinx.com/support/documentation
  25 *
  26 * Xilinx SPI Register Definitions
  27 * [1]: [0]/ip_documentation/xps_spi.pdf
  28 *      page 8, Register Descriptions
  29 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
  30 *      page 7, Register Overview Table
  31 */
  32
  33/* SPI Control Register (spicr), [1] p9, [2] p8 */
  34#define SPICR_LSB_FIRST         BIT(9)
  35#define SPICR_MASTER_INHIBIT    BIT(8)
  36#define SPICR_MANUAL_SS         BIT(7)
  37#define SPICR_RXFIFO_RESEST     BIT(6)
  38#define SPICR_TXFIFO_RESEST     BIT(5)
  39#define SPICR_CPHA              BIT(4)
  40#define SPICR_CPOL              BIT(3)
  41#define SPICR_MASTER_MODE       BIT(2)
  42#define SPICR_SPE               BIT(1)
  43#define SPICR_LOOP              BIT(0)
  44
  45/* SPI Status Register (spisr), [1] p11, [2] p10 */
  46#define SPISR_SLAVE_MODE_SELECT BIT(5)
  47#define SPISR_MODF              BIT(4)
  48#define SPISR_TX_FULL           BIT(3)
  49#define SPISR_TX_EMPTY          BIT(2)
  50#define SPISR_RX_FULL           BIT(1)
  51#define SPISR_RX_EMPTY          BIT(0)
  52
  53/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
  54#define SPIDTR_8BIT_MASK        GENMASK(7, 0)
  55#define SPIDTR_16BIT_MASK       GENMASK(15, 0)
  56#define SPIDTR_32BIT_MASK       GENMASK(31, 0)
  57
  58/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
  59#define SPIDRR_8BIT_MASK        GENMASK(7, 0)
  60#define SPIDRR_16BIT_MASK       GENMASK(15, 0)
  61#define SPIDRR_32BIT_MASK       GENMASK(31, 0)
  62
  63/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
  64#define SPISSR_MASK(cs)         (1 << (cs))
  65#define SPISSR_ACT(cs)          ~SPISSR_MASK(cs)
  66#define SPISSR_OFF              ~0UL
  67
  68/* SPI Software Reset Register (ssr) */
  69#define SPISSR_RESET_VALUE      0x0a
  70
  71#define XILSPI_MAX_XFER_BITS    8
  72#define XILSPI_SPICR_DFLT_ON    (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
  73                                SPICR_SPE)
  74#define XILSPI_SPICR_DFLT_OFF   (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
  75
  76#ifndef CONFIG_XILINX_SPI_IDLE_VAL
  77#define CONFIG_XILINX_SPI_IDLE_VAL      GENMASK(7, 0)
  78#endif
  79
  80#ifndef CONFIG_SYS_XILINX_SPI_LIST
  81#define CONFIG_SYS_XILINX_SPI_LIST      { CONFIG_SYS_SPI_BASE }
  82#endif
  83
  84/* xilinx spi register set */
  85struct xilinx_spi_regs {
  86        u32 __space0__[7];
  87        u32 dgier;      /* Device Global Interrupt Enable Register (DGIER) */
  88        u32 ipisr;      /* IP Interrupt Status Register (IPISR) */
  89        u32 __space1__;
  90        u32 ipier;      /* IP Interrupt Enable Register (IPIER) */
  91        u32 __space2__[5];
  92        u32 srr;        /* Softare Reset Register (SRR) */
  93        u32 __space3__[7];
  94        u32 spicr;      /* SPI Control Register (SPICR) */
  95        u32 spisr;      /* SPI Status Register (SPISR) */
  96        u32 spidtr;     /* SPI Data Transmit Register (SPIDTR) */
  97        u32 spidrr;     /* SPI Data Receive Register (SPIDRR) */
  98        u32 spissr;     /* SPI Slave Select Register (SPISSR) */
  99        u32 spitfor;    /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
 100        u32 spirfor;    /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
 101};
 102
 103/* xilinx spi priv */
 104struct xilinx_spi_priv {
 105        struct xilinx_spi_regs *regs;
 106        unsigned int freq;
 107        unsigned int mode;
 108};
 109
 110static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 111static int xilinx_spi_probe(struct udevice *bus)
 112{
 113        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 114        struct xilinx_spi_regs *regs = priv->regs;
 115
 116        priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
 117
 118        writel(SPISSR_RESET_VALUE, &regs->srr);
 119
 120        return 0;
 121}
 122
 123static void spi_cs_activate(struct udevice *dev, uint cs)
 124{
 125        struct udevice *bus = dev_get_parent(dev);
 126        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 127        struct xilinx_spi_regs *regs = priv->regs;
 128
 129        writel(SPISSR_ACT(cs), &regs->spissr);
 130}
 131
 132static void spi_cs_deactivate(struct udevice *dev)
 133{
 134        struct udevice *bus = dev_get_parent(dev);
 135        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 136        struct xilinx_spi_regs *regs = priv->regs;
 137
 138        writel(SPISSR_OFF, &regs->spissr);
 139}
 140
 141static int xilinx_spi_claim_bus(struct udevice *dev)
 142{
 143        struct udevice *bus = dev_get_parent(dev);
 144        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 145        struct xilinx_spi_regs *regs = priv->regs;
 146
 147        writel(SPISSR_OFF, &regs->spissr);
 148        writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
 149
 150        return 0;
 151}
 152
 153static int xilinx_spi_release_bus(struct udevice *dev)
 154{
 155        struct udevice *bus = dev_get_parent(dev);
 156        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 157        struct xilinx_spi_regs *regs = priv->regs;
 158
 159        writel(SPISSR_OFF, &regs->spissr);
 160        writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
 161
 162        return 0;
 163}
 164
 165static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
 166                            const void *dout, void *din, unsigned long flags)
 167{
 168        struct udevice *bus = dev_get_parent(dev);
 169        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 170        struct xilinx_spi_regs *regs = priv->regs;
 171        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 172        /* assume spi core configured to do 8 bit transfers */
 173        unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
 174        const unsigned char *txp = dout;
 175        unsigned char *rxp = din;
 176        unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
 177        unsigned global_timeout;
 178
 179        debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
 180              bus->seq, slave_plat->cs, bitlen, bytes, flags);
 181
 182        if (bitlen == 0)
 183                goto done;
 184
 185        if (bitlen % XILSPI_MAX_XFER_BITS) {
 186                printf("XILSPI warning: Not a multiple of %d bits\n",
 187                       XILSPI_MAX_XFER_BITS);
 188                flags |= SPI_XFER_END;
 189                goto done;
 190        }
 191
 192        /* empty read buffer */
 193        while (rxecount && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
 194                readl(&regs->spidrr);
 195                rxecount--;
 196        }
 197
 198        if (!rxecount) {
 199                printf("XILSPI error: Rx buffer not empty\n");
 200                return -1;
 201        }
 202
 203        if (flags & SPI_XFER_BEGIN)
 204                spi_cs_activate(dev, slave_plat->cs);
 205
 206        /* at least 1usec or greater, leftover 1 */
 207        global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
 208                        (XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1;
 209
 210        while (bytes--) {
 211                unsigned timeout = global_timeout;
 212                /* get Tx element from data out buffer and count up */
 213                unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
 214                debug("spi_xfer: tx:%x ", d);
 215
 216                /* write out and wait for processing (receive data) */
 217                writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
 218                while (timeout && readl(&regs->spisr)
 219                                                & SPISR_RX_EMPTY) {
 220                        timeout--;
 221                        udelay(1);
 222                }
 223
 224                if (!timeout) {
 225                        printf("XILSPI error: Xfer timeout\n");
 226                        return -1;
 227                }
 228
 229                /* read Rx element and push into data in buffer */
 230                d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
 231                if (rxp)
 232                        *rxp++ = d;
 233                debug("spi_xfer: rx:%x\n", d);
 234        }
 235
 236 done:
 237        if (flags & SPI_XFER_END)
 238                spi_cs_deactivate(dev);
 239
 240        return 0;
 241}
 242
 243static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
 244{
 245        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 246
 247        priv->freq = speed;
 248
 249        debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
 250              priv->freq);
 251
 252        return 0;
 253}
 254
 255static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
 256{
 257        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 258        struct xilinx_spi_regs *regs = priv->regs;
 259        uint32_t spicr;
 260
 261        spicr = readl(&regs->spicr);
 262        if (mode & SPI_LSB_FIRST)
 263                spicr |= SPICR_LSB_FIRST;
 264        if (mode & SPI_CPHA)
 265                spicr |= SPICR_CPHA;
 266        if (mode & SPI_CPOL)
 267                spicr |= SPICR_CPOL;
 268        if (mode & SPI_LOOP)
 269                spicr |= SPICR_LOOP;
 270
 271        writel(spicr, &regs->spicr);
 272        priv->mode = mode;
 273
 274        debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
 275              priv->mode);
 276
 277        return 0;
 278}
 279
 280static const struct dm_spi_ops xilinx_spi_ops = {
 281        .claim_bus      = xilinx_spi_claim_bus,
 282        .release_bus    = xilinx_spi_release_bus,
 283        .xfer           = xilinx_spi_xfer,
 284        .set_speed      = xilinx_spi_set_speed,
 285        .set_mode       = xilinx_spi_set_mode,
 286};
 287
 288static const struct udevice_id xilinx_spi_ids[] = {
 289        { .compatible = "xlnx,xps-spi-2.00.a" },
 290        { .compatible = "xlnx,xps-spi-2.00.b" },
 291        { }
 292};
 293
 294U_BOOT_DRIVER(xilinx_spi) = {
 295        .name   = "xilinx_spi",
 296        .id     = UCLASS_SPI,
 297        .of_match = xilinx_spi_ids,
 298        .ops    = &xilinx_spi_ops,
 299        .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
 300        .probe  = xilinx_spi_probe,
 301};
 302