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20static u8 clear_feature_num;
21int clear_feature_flag;
22
23
24#define GET_MAX_LUN_REQUEST 0xFE
25#define BOT_RESET_REQUEST 0xFF
26
27static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
28{
29 u32 ep_ctrl;
30
31 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
32 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
33
34 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
35 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
36 ®->in_endp[EP0_CON].diepctl);
37
38 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
39 __func__, readl(®->in_endp[EP0_CON].diepctl));
40 dev->ep0state = WAIT_FOR_IN_COMPLETE;
41}
42
43static void dwc2_udc_pre_setup(void)
44{
45 u32 ep_ctrl;
46
47 debug_cond(DEBUG_IN_EP,
48 "%s : Prepare Setup packets.\n", __func__);
49
50 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
51 ®->out_endp[EP0_CON].doeptsiz);
52 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
53
54 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
55 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
56
57 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
58 __func__, readl(®->in_endp[EP0_CON].diepctl));
59 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
60 __func__, readl(®->out_endp[EP0_CON].doepctl));
61
62}
63
64static inline void dwc2_ep0_complete_out(void)
65{
66 u32 ep_ctrl;
67
68 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
69 __func__, readl(®->in_endp[EP0_CON].diepctl));
70 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
71 __func__, readl(®->out_endp[EP0_CON].doepctl));
72
73 debug_cond(DEBUG_IN_EP,
74 "%s : Prepare Complete Out packet.\n", __func__);
75
76 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
77 ®->out_endp[EP0_CON].doeptsiz);
78 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
79
80 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
81 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
82 ®->out_endp[EP0_CON].doepctl);
83
84 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
85 __func__, readl(®->in_endp[EP0_CON].diepctl));
86 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
87 __func__, readl(®->out_endp[EP0_CON].doepctl));
88
89}
90
91
92static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
93{
94 u32 *buf, ctrl;
95 u32 length, pktcnt;
96 u32 ep_num = ep_index(ep);
97
98 buf = req->req.buf + req->req.actual;
99 length = min_t(u32, req->req.length - req->req.actual,
100 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
101
102 ep->len = length;
103 ep->dma_buf = buf;
104
105 if (ep_num == EP0_CON || length == 0)
106 pktcnt = 1;
107 else
108 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
109
110 ctrl = readl(®->out_endp[ep_num].doepctl);
111
112 invalidate_dcache_range((unsigned long) ep->dma_buf,
113 (unsigned long) ep->dma_buf +
114 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
115
116 writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma);
117 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
118 ®->out_endp[ep_num].doeptsiz);
119 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
120
121 debug_cond(DEBUG_OUT_EP != 0,
122 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
123 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
124 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
125 __func__, ep_num,
126 readl(®->out_endp[ep_num].doepdma),
127 readl(®->out_endp[ep_num].doeptsiz),
128 readl(®->out_endp[ep_num].doepctl),
129 buf, pktcnt, length);
130 return 0;
131
132}
133
134static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
135{
136 u32 *buf, ctrl = 0;
137 u32 length, pktcnt;
138 u32 ep_num = ep_index(ep);
139
140 buf = req->req.buf + req->req.actual;
141 length = req->req.length - req->req.actual;
142
143 if (ep_num == EP0_CON)
144 length = min(length, (u32)ep_maxpacket(ep));
145
146 ep->len = length;
147 ep->dma_buf = buf;
148
149 flush_dcache_range((unsigned long) ep->dma_buf,
150 (unsigned long) ep->dma_buf +
151 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
152
153 if (length == 0)
154 pktcnt = 1;
155 else
156 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
157
158
159 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
160 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
161 while (readl(®->grstctl) & TX_FIFO_FLUSH)
162 ;
163
164 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
165 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
166 ®->in_endp[ep_num].dieptsiz);
167
168 ctrl = readl(®->in_endp[ep_num].diepctl);
169
170
171 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
172 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
173
174
175 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
176
177 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
178
179 debug_cond(DEBUG_IN_EP,
180 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
181 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
182 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
183 __func__, ep_num,
184 readl(®->in_endp[ep_num].diepdma),
185 readl(®->in_endp[ep_num].dieptsiz),
186 readl(®->in_endp[ep_num].diepctl),
187 buf, pktcnt, length);
188
189 return length;
190}
191
192static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
193{
194 struct dwc2_ep *ep = &dev->ep[ep_num];
195 struct dwc2_request *req = NULL;
196 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
197
198 if (list_empty(&ep->queue)) {
199 debug_cond(DEBUG_OUT_EP != 0,
200 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
201 __func__, ep_num);
202 return;
203
204 }
205
206 req = list_entry(ep->queue.next, struct dwc2_request, queue);
207 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
208
209 if (ep_num == EP0_CON)
210 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
211 else
212 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
213
214 xfer_size = ep->len - xfer_size;
215
216
217
218
219
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222
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224
225
226
227
228
229
230 invalidate_dcache_range((unsigned long) ep->dma_buf,
231 (unsigned long) ep->dma_buf +
232 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
233
234 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
235 is_short = !!(xfer_size % ep->ep.maxpacket);
236
237 debug_cond(DEBUG_OUT_EP != 0,
238 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
239 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
240 __func__, ep_num, req->req.actual, req->req.length,
241 is_short, ep_tsr, req->req.length - req->req.actual);
242
243 if (is_short || req->req.actual == req->req.length) {
244 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
245 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
246 dwc2_udc_ep0_zlp(dev);
247
248 dev->ep0state = WAIT_FOR_IN_COMPLETE;
249 } else {
250 done(ep, req, 0);
251
252 if (!list_empty(&ep->queue)) {
253 req = list_entry(ep->queue.next,
254 struct dwc2_request, queue);
255 debug_cond(DEBUG_OUT_EP != 0,
256 "%s: Next Rx request start...\n",
257 __func__);
258 setdma_rx(ep, req);
259 }
260 }
261 } else
262 setdma_rx(ep, req);
263}
264
265static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
266{
267 struct dwc2_ep *ep = &dev->ep[ep_num];
268 struct dwc2_request *req;
269 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
270 u32 last;
271
272 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
273 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
274 dwc2_ep0_complete_out();
275 return;
276 }
277
278 if (list_empty(&ep->queue)) {
279 debug_cond(DEBUG_IN_EP,
280 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
281 __func__, ep_num);
282 return;
283
284 }
285
286 req = list_entry(ep->queue.next, struct dwc2_request, queue);
287
288 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
289
290 xfer_size = ep->len;
291 is_short = (xfer_size < ep->ep.maxpacket);
292 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
293
294 debug_cond(DEBUG_IN_EP,
295 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
296 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
297 __func__, ep_num, req->req.actual, req->req.length,
298 is_short, ep_tsr, req->req.length - req->req.actual);
299
300 if (ep_num == 0) {
301 if (dev->ep0state == DATA_STATE_XMIT) {
302 debug_cond(DEBUG_IN_EP,
303 "%s: ep_num = %d, ep0stat =="
304 "DATA_STATE_XMIT\n",
305 __func__, ep_num);
306 last = write_fifo_ep0(ep, req);
307 if (last)
308 dev->ep0state = WAIT_FOR_COMPLETE;
309 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
310 debug_cond(DEBUG_IN_EP,
311 "%s: ep_num = %d, completing request\n",
312 __func__, ep_num);
313 done(ep, req, 0);
314 dev->ep0state = WAIT_FOR_SETUP;
315 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
316 debug_cond(DEBUG_IN_EP,
317 "%s: ep_num = %d, completing request\n",
318 __func__, ep_num);
319 done(ep, req, 0);
320 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
321 dwc2_ep0_complete_out();
322 } else {
323 debug_cond(DEBUG_IN_EP,
324 "%s: ep_num = %d, invalid ep state\n",
325 __func__, ep_num);
326 }
327 return;
328 }
329
330 if (req->req.actual == req->req.length)
331 done(ep, req, 0);
332
333 if (!list_empty(&ep->queue)) {
334 req = list_entry(ep->queue.next, struct dwc2_request, queue);
335 debug_cond(DEBUG_IN_EP,
336 "%s: Next Tx request start...\n", __func__);
337 setdma_tx(ep, req);
338 }
339}
340
341static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
342{
343 struct dwc2_ep *ep = &dev->ep[ep_num];
344 struct dwc2_request *req;
345
346 debug_cond(DEBUG_IN_EP,
347 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
348
349 if (!list_empty(&ep->queue)) {
350 req = list_entry(ep->queue.next, struct dwc2_request, queue);
351 debug_cond(DEBUG_IN_EP,
352 "%s: Next Tx request(0x%p) start...\n",
353 __func__, req);
354
355 if (ep_is_in(ep))
356 setdma_tx(ep, req);
357 else
358 setdma_rx(ep, req);
359 } else {
360 debug_cond(DEBUG_IN_EP,
361 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
362
363 return;
364 }
365
366}
367
368static void process_ep_in_intr(struct dwc2_udc *dev)
369{
370 u32 ep_intr, ep_intr_status;
371 u8 ep_num = 0;
372
373 ep_intr = readl(®->daint);
374 debug_cond(DEBUG_IN_EP,
375 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
376
377 ep_intr &= DAINT_MASK;
378
379 while (ep_intr) {
380 if (ep_intr & DAINT_IN_EP_INT(1)) {
381 ep_intr_status = readl(®->in_endp[ep_num].diepint);
382 debug_cond(DEBUG_IN_EP,
383 "\tEP%d-IN : DIEPINT = 0x%x\n",
384 ep_num, ep_intr_status);
385
386
387 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
388
389 if (ep_intr_status & TRANSFER_DONE) {
390 complete_tx(dev, ep_num);
391
392 if (ep_num == 0) {
393 if (dev->ep0state ==
394 WAIT_FOR_IN_COMPLETE)
395 dev->ep0state = WAIT_FOR_SETUP;
396
397 if (dev->ep0state == WAIT_FOR_SETUP)
398 dwc2_udc_pre_setup();
399
400
401
402 if (clear_feature_flag == 1) {
403 dwc2_udc_check_tx_queue(dev,
404 clear_feature_num);
405 clear_feature_flag = 0;
406 }
407 }
408 }
409 }
410 ep_num++;
411 ep_intr >>= 1;
412 }
413}
414
415static void process_ep_out_intr(struct dwc2_udc *dev)
416{
417 u32 ep_intr, ep_intr_status;
418 u8 ep_num = 0;
419
420 ep_intr = readl(®->daint);
421 debug_cond(DEBUG_OUT_EP != 0,
422 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
423 __func__, ep_intr);
424
425 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
426
427 while (ep_intr) {
428 if (ep_intr & 0x1) {
429 ep_intr_status = readl(®->out_endp[ep_num].doepint);
430 debug_cond(DEBUG_OUT_EP != 0,
431 "\tEP%d-OUT : DOEPINT = 0x%x\n",
432 ep_num, ep_intr_status);
433
434
435 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
436
437 if (ep_num == 0) {
438 if (ep_intr_status & TRANSFER_DONE) {
439 if (dev->ep0state !=
440 WAIT_FOR_OUT_COMPLETE)
441 complete_rx(dev, ep_num);
442 else {
443 dev->ep0state = WAIT_FOR_SETUP;
444 dwc2_udc_pre_setup();
445 }
446 }
447
448 if (ep_intr_status &
449 CTRL_OUT_EP_SETUP_PHASE_DONE) {
450 debug_cond(DEBUG_OUT_EP != 0,
451 "SETUP packet arrived\n");
452 dwc2_handle_ep0(dev);
453 }
454 } else {
455 if (ep_intr_status & TRANSFER_DONE)
456 complete_rx(dev, ep_num);
457 }
458 }
459 ep_num++;
460 ep_intr >>= 1;
461 }
462}
463
464
465
466
467static int dwc2_udc_irq(int irq, void *_dev)
468{
469 struct dwc2_udc *dev = _dev;
470 u32 intr_status;
471 u32 usb_status, gintmsk;
472 unsigned long flags = 0;
473
474 spin_lock_irqsave(&dev->lock, flags);
475
476 intr_status = readl(®->gintsts);
477 gintmsk = readl(®->gintmsk);
478
479 debug_cond(DEBUG_ISR,
480 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
481 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
482 __func__, intr_status, state_names[dev->ep0state], gintmsk,
483 readl(®->daint), readl(®->daintmsk));
484
485 if (!intr_status) {
486 spin_unlock_irqrestore(&dev->lock, flags);
487 return IRQ_HANDLED;
488 }
489
490 if (intr_status & INT_ENUMDONE) {
491 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
492
493 writel(INT_ENUMDONE, ®->gintsts);
494 usb_status = (readl(®->dsts) & 0x6);
495
496 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
497 debug_cond(DEBUG_ISR,
498 "\t\tFull Speed Detection\n");
499 set_max_pktsize(dev, USB_SPEED_FULL);
500
501 } else {
502 debug_cond(DEBUG_ISR,
503 "\t\tHigh Speed Detection : 0x%x\n",
504 usb_status);
505 set_max_pktsize(dev, USB_SPEED_HIGH);
506 }
507 }
508
509 if (intr_status & INT_EARLY_SUSPEND) {
510 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
511 writel(INT_EARLY_SUSPEND, ®->gintsts);
512 }
513
514 if (intr_status & INT_SUSPEND) {
515 usb_status = readl(®->dsts);
516 debug_cond(DEBUG_ISR,
517 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
518 writel(INT_SUSPEND, ®->gintsts);
519
520 if (dev->gadget.speed != USB_SPEED_UNKNOWN
521 && dev->driver) {
522 if (dev->driver->suspend)
523 dev->driver->suspend(&dev->gadget);
524
525
526 if (dev->driver->disconnect) {
527 spin_unlock_irqrestore(&dev->lock, flags);
528 dev->driver->disconnect(&dev->gadget);
529 spin_lock_irqsave(&dev->lock, flags);
530 }
531 }
532 }
533
534 if (intr_status & INT_RESUME) {
535 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
536 writel(INT_RESUME, ®->gintsts);
537
538 if (dev->gadget.speed != USB_SPEED_UNKNOWN
539 && dev->driver
540 && dev->driver->resume) {
541
542 dev->driver->resume(&dev->gadget);
543 }
544 }
545
546 if (intr_status & INT_RESET) {
547 usb_status = readl(®->gotgctl);
548 debug_cond(DEBUG_ISR,
549 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
550 writel(INT_RESET, ®->gintsts);
551
552 if ((usb_status & 0xc0000) == (0x3 << 18)) {
553 if (reset_available) {
554 debug_cond(DEBUG_ISR,
555 "\t\tOTG core got reset (%d)!!\n",
556 reset_available);
557 reconfig_usbd(dev);
558 dev->ep0state = WAIT_FOR_SETUP;
559 reset_available = 0;
560 dwc2_udc_pre_setup();
561 } else
562 reset_available = 1;
563
564 } else {
565 reset_available = 1;
566 debug_cond(DEBUG_ISR,
567 "\t\tRESET handling skipped\n");
568 }
569 }
570
571 if (intr_status & INT_IN_EP)
572 process_ep_in_intr(dev);
573
574 if (intr_status & INT_OUT_EP)
575 process_ep_out_intr(dev);
576
577 spin_unlock_irqrestore(&dev->lock, flags);
578
579 return IRQ_HANDLED;
580}
581
582
583
584
585static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
586 gfp_t gfp_flags)
587{
588 struct dwc2_request *req;
589 struct dwc2_ep *ep;
590 struct dwc2_udc *dev;
591 unsigned long flags = 0;
592 u32 ep_num, gintsts;
593
594 req = container_of(_req, struct dwc2_request, req);
595 if (unlikely(!_req || !_req->complete || !_req->buf
596 || !list_empty(&req->queue))) {
597
598 debug("%s: bad params\n", __func__);
599 return -EINVAL;
600 }
601
602 ep = container_of(_ep, struct dwc2_ep, ep);
603
604 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
605
606 debug("%s: bad ep: %s, %d, %p\n", __func__,
607 ep->ep.name, !ep->desc, _ep);
608 return -EINVAL;
609 }
610
611 ep_num = ep_index(ep);
612 dev = ep->dev;
613 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
614
615 debug("%s: bogus device state %p\n", __func__, dev->driver);
616 return -ESHUTDOWN;
617 }
618
619 spin_lock_irqsave(&dev->lock, flags);
620
621 _req->status = -EINPROGRESS;
622 _req->actual = 0;
623
624
625 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
626 "Q empty = %d, stopped = %d\n",
627 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
628 _req, _req->length, _req->buf,
629 list_empty(&ep->queue), ep->stopped);
630
631#ifdef DEBUG
632 {
633 int i, len = _req->length;
634
635 printf("pkt = ");
636 if (len > 64)
637 len = 64;
638 for (i = 0; i < len; i++) {
639 printf("%02x", ((u8 *)_req->buf)[i]);
640 if ((i & 7) == 7)
641 printf(" ");
642 }
643 printf("\n");
644 }
645#endif
646
647 if (list_empty(&ep->queue) && !ep->stopped) {
648
649 if (ep_num == 0) {
650
651 list_add_tail(&req->queue, &ep->queue);
652 dwc2_ep0_kick(dev, ep);
653 req = 0;
654
655 } else if (ep_is_in(ep)) {
656 gintsts = readl(®->gintsts);
657 debug_cond(DEBUG_IN_EP,
658 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
659 __func__, gintsts);
660
661 setdma_tx(ep, req);
662 } else {
663 gintsts = readl(®->gintsts);
664 debug_cond(DEBUG_OUT_EP != 0,
665 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
666 __func__, gintsts);
667
668 setdma_rx(ep, req);
669 }
670 }
671
672
673 if (likely(req != 0))
674 list_add_tail(&req->queue, &ep->queue);
675
676 spin_unlock_irqrestore(&dev->lock, flags);
677
678 return 0;
679}
680
681
682
683
684
685
686static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
687{
688 u32 max;
689 unsigned count;
690 int is_last;
691
692 max = ep_maxpacket(ep);
693
694 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
695
696 count = setdma_tx(ep, req);
697
698
699 if (likely(count != max))
700 is_last = 1;
701 else {
702 if (likely(req->req.length != req->req.actual + count)
703 || req->req.zero)
704 is_last = 0;
705 else
706 is_last = 1;
707 }
708
709 debug_cond(DEBUG_EP0 != 0,
710 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
711 ep->ep.name, count,
712 is_last ? "/L" : "",
713 req->req.length - req->req.actual - count, req);
714
715
716 if (is_last) {
717 ep->dev->ep0state = WAIT_FOR_SETUP;
718 return 1;
719 }
720
721 return 0;
722}
723
724static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
725{
726 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
727 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
728
729 debug_cond(DEBUG_EP0 != 0,
730 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
731 max, ep_index(ep), cp);
732
733 return max;
734}
735
736
737
738
739
740
741
742
743static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
744{
745 u32 ctrl = readl(®->dcfg);
746 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
747
748 dwc2_udc_ep0_zlp(dev);
749
750 debug_cond(DEBUG_EP0 != 0,
751 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
752 __func__, address, readl(®->dcfg));
753
754 dev->usb_address = address;
755}
756
757static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
758{
759 struct dwc2_udc *dev;
760 u32 ep_ctrl = 0;
761
762 dev = ep->dev;
763 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
764
765
766 if (ep_ctrl & DEPCTL_EPENA)
767 ep_ctrl |= DEPCTL_EPDIS;
768
769 ep_ctrl |= DEPCTL_STALL;
770
771 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
772
773 debug_cond(DEBUG_EP0 != 0,
774 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
775 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
776
777
778
779
780 dev->ep0state = WAIT_FOR_SETUP;
781
782 dwc2_udc_pre_setup();
783}
784
785static void dwc2_ep0_read(struct dwc2_udc *dev)
786{
787 struct dwc2_request *req;
788 struct dwc2_ep *ep = &dev->ep[0];
789
790 if (!list_empty(&ep->queue)) {
791 req = list_entry(ep->queue.next, struct dwc2_request, queue);
792
793 } else {
794 debug("%s: ---> BUG\n", __func__);
795 BUG();
796 return;
797 }
798
799 debug_cond(DEBUG_EP0 != 0,
800 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
801 __func__, req, req->req.length, req->req.actual);
802
803 if (req->req.length == 0) {
804
805
806
807 ep->len = 0;
808 dwc2_udc_ep0_zlp(dev);
809
810 debug_cond(DEBUG_EP0 != 0,
811 "%s: req.length = 0, bRequest = %d\n",
812 __func__, usb_ctrl->bRequest);
813 return;
814 }
815
816 setdma_rx(ep, req);
817}
818
819
820
821
822static int dwc2_ep0_write(struct dwc2_udc *dev)
823{
824 struct dwc2_request *req;
825 struct dwc2_ep *ep = &dev->ep[0];
826 int ret, need_zlp = 0;
827
828 if (list_empty(&ep->queue))
829 req = 0;
830 else
831 req = list_entry(ep->queue.next, struct dwc2_request, queue);
832
833 if (!req) {
834 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
835 return 0;
836 }
837
838 debug_cond(DEBUG_EP0 != 0,
839 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
840 __func__, req, req->req.length, req->req.actual);
841
842 if (req->req.length - req->req.actual == ep0_fifo_size) {
843
844
845 need_zlp = 1;
846 }
847
848 ret = write_fifo_ep0(ep, req);
849
850 if ((ret == 1) && !need_zlp) {
851
852 dev->ep0state = WAIT_FOR_COMPLETE;
853 debug_cond(DEBUG_EP0 != 0,
854 "%s: finished, waiting for status\n", __func__);
855
856 } else {
857 dev->ep0state = DATA_STATE_XMIT;
858 debug_cond(DEBUG_EP0 != 0,
859 "%s: not finished\n", __func__);
860 }
861
862 return 1;
863}
864
865static int dwc2_udc_get_status(struct dwc2_udc *dev,
866 struct usb_ctrlrequest *crq)
867{
868 u8 ep_num = crq->wIndex & 0x7F;
869 u16 g_status = 0;
870 u32 ep_ctrl;
871
872 debug_cond(DEBUG_SETUP != 0,
873 "%s: *** USB_REQ_GET_STATUS\n", __func__);
874 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
875 switch (crq->bRequestType & USB_RECIP_MASK) {
876 case USB_RECIP_INTERFACE:
877 g_status = 0;
878 debug_cond(DEBUG_SETUP != 0,
879 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
880 g_status);
881 break;
882
883 case USB_RECIP_DEVICE:
884 g_status = 0x1;
885 debug_cond(DEBUG_SETUP != 0,
886 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
887 g_status);
888 break;
889
890 case USB_RECIP_ENDPOINT:
891 if (crq->wLength > 2) {
892 debug_cond(DEBUG_SETUP != 0,
893 "\tGET_STATUS:Not support EP or wLength\n");
894 return 1;
895 }
896
897 g_status = dev->ep[ep_num].stopped;
898 debug_cond(DEBUG_SETUP != 0,
899 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
900 g_status);
901
902 break;
903
904 default:
905 return 1;
906 }
907
908 memcpy(usb_ctrl, &g_status, sizeof(g_status));
909
910 flush_dcache_range((unsigned long) usb_ctrl,
911 (unsigned long) usb_ctrl +
912 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
913
914 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
915 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
916 ®->in_endp[EP0_CON].dieptsiz);
917
918 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
919 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
920 ®->in_endp[EP0_CON].diepctl);
921 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
922
923 return 0;
924}
925
926static void dwc2_udc_set_nak(struct dwc2_ep *ep)
927{
928 u8 ep_num;
929 u32 ep_ctrl = 0;
930
931 ep_num = ep_index(ep);
932 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
933
934 if (ep_is_in(ep)) {
935 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
936 ep_ctrl |= DEPCTL_SNAK;
937 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
938 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
939 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
940 } else {
941 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
942 ep_ctrl |= DEPCTL_SNAK;
943 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
944 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
945 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
946 }
947
948 return;
949}
950
951
952static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
953{
954 u8 ep_num;
955 u32 ep_ctrl = 0;
956
957 ep_num = ep_index(ep);
958 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
959
960 if (ep_is_in(ep)) {
961 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
962
963
964 if (ep_ctrl & DEPCTL_EPENA)
965 ep_ctrl |= DEPCTL_EPDIS;
966
967 ep_ctrl |= DEPCTL_STALL;
968
969 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
970 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
971 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
972
973 } else {
974 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
975
976
977 ep_ctrl |= DEPCTL_STALL;
978
979 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
980 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
981 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
982 }
983
984 return;
985}
986
987static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
988{
989 u8 ep_num;
990 u32 ep_ctrl = 0;
991
992 ep_num = ep_index(ep);
993 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
994
995 if (ep_is_in(ep)) {
996 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
997
998
999 ep_ctrl &= ~DEPCTL_STALL;
1000
1001
1002
1003
1004
1005
1006
1007 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1008 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1009 ep_ctrl |= DEPCTL_SETD0PID;
1010 }
1011
1012 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1013 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1014 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1015
1016 } else {
1017 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1018
1019
1020 ep_ctrl &= ~DEPCTL_STALL;
1021
1022 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1023 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1024 ep_ctrl |= DEPCTL_SETD0PID;
1025 }
1026
1027 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1028 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1029 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1030 }
1031
1032 return;
1033}
1034
1035static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1036{
1037 struct dwc2_ep *ep;
1038 struct dwc2_udc *dev;
1039 unsigned long flags = 0;
1040 u8 ep_num;
1041
1042 ep = container_of(_ep, struct dwc2_ep, ep);
1043 ep_num = ep_index(ep);
1044
1045 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1046 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1047 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1048 return -EINVAL;
1049 }
1050
1051
1052
1053 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1054 debug("%s: %s queue not empty, req = %p\n",
1055 __func__, ep->ep.name,
1056 list_entry(ep->queue.next, struct dwc2_request, queue));
1057
1058 return -EAGAIN;
1059 }
1060
1061 dev = ep->dev;
1062 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1063
1064 spin_lock_irqsave(&dev->lock, flags);
1065
1066 if (value == 0) {
1067 ep->stopped = 0;
1068 dwc2_udc_ep_clear_stall(ep);
1069 } else {
1070 if (ep_num == 0)
1071 dev->ep0state = WAIT_FOR_SETUP;
1072
1073 ep->stopped = 1;
1074 dwc2_udc_ep_set_stall(ep);
1075 }
1076
1077 spin_unlock_irqrestore(&dev->lock, flags);
1078
1079 return 0;
1080}
1081
1082static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1083{
1084 u8 ep_num;
1085 u32 ep_ctrl = 0, daintmsk = 0;
1086
1087 ep_num = ep_index(ep);
1088
1089
1090 if (ep_is_in(ep)) {
1091 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1092 daintmsk = 1 << ep_num;
1093 } else {
1094 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1095 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1096 }
1097
1098 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1099 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1100
1101
1102
1103 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1104 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1105 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1106 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1107 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1108 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1109
1110 if (ep_is_in(ep)) {
1111 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1112 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1113 __func__, ep_num, ep_num,
1114 readl(®->in_endp[ep_num].diepctl));
1115 } else {
1116 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1117 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1118 __func__, ep_num, ep_num,
1119 readl(®->out_endp[ep_num].doepctl));
1120 }
1121 }
1122
1123
1124 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1125 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1126
1127}
1128
1129static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1130{
1131 struct dwc2_udc *dev;
1132 struct dwc2_ep *ep;
1133 u8 ep_num;
1134
1135 ep = container_of(_ep, struct dwc2_ep, ep);
1136 ep_num = ep_index(ep);
1137
1138 dev = ep->dev;
1139 debug_cond(DEBUG_SETUP != 0,
1140 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1141 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1142
1143 if (usb_ctrl->wLength != 0) {
1144 debug_cond(DEBUG_SETUP != 0,
1145 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1146 return 1;
1147 }
1148
1149 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1150 case USB_RECIP_DEVICE:
1151 switch (usb_ctrl->wValue) {
1152 case USB_DEVICE_REMOTE_WAKEUP:
1153 debug_cond(DEBUG_SETUP != 0,
1154 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1155 break;
1156
1157 case USB_DEVICE_TEST_MODE:
1158 debug_cond(DEBUG_SETUP != 0,
1159 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1160
1161 break;
1162 }
1163
1164 dwc2_udc_ep0_zlp(dev);
1165 break;
1166
1167 case USB_RECIP_ENDPOINT:
1168 debug_cond(DEBUG_SETUP != 0,
1169 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1170 usb_ctrl->wValue);
1171
1172 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1173 if (ep_num == 0) {
1174 dwc2_udc_ep0_set_stall(ep);
1175 return 0;
1176 }
1177
1178 dwc2_udc_ep0_zlp(dev);
1179
1180 dwc2_udc_ep_clear_stall(ep);
1181 dwc2_udc_ep_activate(ep);
1182 ep->stopped = 0;
1183
1184 clear_feature_num = ep_num;
1185 clear_feature_flag = 1;
1186 }
1187 break;
1188 }
1189
1190 return 0;
1191}
1192
1193static int dwc2_udc_set_feature(struct usb_ep *_ep)
1194{
1195 struct dwc2_udc *dev;
1196 struct dwc2_ep *ep;
1197 u8 ep_num;
1198
1199 ep = container_of(_ep, struct dwc2_ep, ep);
1200 ep_num = ep_index(ep);
1201 dev = ep->dev;
1202
1203 debug_cond(DEBUG_SETUP != 0,
1204 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1205 __func__, ep_num);
1206
1207 if (usb_ctrl->wLength != 0) {
1208 debug_cond(DEBUG_SETUP != 0,
1209 "\tSET_FEATURE: wLength is not zero.....\n");
1210 return 1;
1211 }
1212
1213 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1214 case USB_RECIP_DEVICE:
1215 switch (usb_ctrl->wValue) {
1216 case USB_DEVICE_REMOTE_WAKEUP:
1217 debug_cond(DEBUG_SETUP != 0,
1218 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1219 break;
1220 case USB_DEVICE_B_HNP_ENABLE:
1221 debug_cond(DEBUG_SETUP != 0,
1222 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1223 break;
1224
1225 case USB_DEVICE_A_HNP_SUPPORT:
1226
1227 debug_cond(DEBUG_SETUP != 0,
1228 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1229 break;
1230
1231 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1232
1233 debug_cond(DEBUG_SETUP != 0,
1234 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1235 break;
1236 }
1237
1238 dwc2_udc_ep0_zlp(dev);
1239 return 0;
1240
1241 case USB_RECIP_INTERFACE:
1242 debug_cond(DEBUG_SETUP != 0,
1243 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1244 break;
1245
1246 case USB_RECIP_ENDPOINT:
1247 debug_cond(DEBUG_SETUP != 0,
1248 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1249 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1250 if (ep_num == 0) {
1251 dwc2_udc_ep0_set_stall(ep);
1252 return 0;
1253 }
1254 ep->stopped = 1;
1255 dwc2_udc_ep_set_stall(ep);
1256 }
1257
1258 dwc2_udc_ep0_zlp(dev);
1259 return 0;
1260 }
1261
1262 return 1;
1263}
1264
1265
1266
1267
1268static void dwc2_ep0_setup(struct dwc2_udc *dev)
1269{
1270 struct dwc2_ep *ep = &dev->ep[0];
1271 int i;
1272 u8 ep_num;
1273
1274
1275 nuke(ep, -EPROTO);
1276
1277
1278 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
1279
1280 debug_cond(DEBUG_SETUP != 0,
1281 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1282 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1283 __func__, usb_ctrl->bRequestType,
1284 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1285 usb_ctrl->bRequest,
1286 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1287
1288#ifdef DEBUG
1289 {
1290 int i, len = sizeof(*usb_ctrl);
1291 char *p = (char *)usb_ctrl;
1292
1293 printf("pkt = ");
1294 for (i = 0; i < len; i++) {
1295 printf("%02x", ((u8 *)p)[i]);
1296 if ((i & 7) == 7)
1297 printf(" ");
1298 }
1299 printf("\n");
1300 }
1301#endif
1302
1303 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1304 usb_ctrl->wLength != 1) {
1305 debug_cond(DEBUG_SETUP != 0,
1306 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1307 __func__);
1308 debug_cond(DEBUG_SETUP != 0,
1309 "wLength = %d, setup returned\n",
1310 usb_ctrl->wLength);
1311
1312 dwc2_udc_ep0_set_stall(ep);
1313 dev->ep0state = WAIT_FOR_SETUP;
1314
1315 return;
1316 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1317 usb_ctrl->wLength != 0) {
1318
1319 debug_cond(DEBUG_SETUP != 0,
1320 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1321 __func__, usb_ctrl->wLength);
1322
1323 dwc2_udc_ep0_set_stall(ep);
1324 dev->ep0state = WAIT_FOR_SETUP;
1325
1326 return;
1327 }
1328
1329
1330 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1331 ep->bEndpointAddress |= USB_DIR_IN;
1332 } else {
1333 ep->bEndpointAddress &= ~USB_DIR_IN;
1334 }
1335
1336 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1337 == USB_TYPE_STANDARD;
1338
1339 dev->req_pending = 1;
1340
1341
1342 if (dev->req_std) {
1343 switch (usb_ctrl->bRequest) {
1344 case USB_REQ_SET_ADDRESS:
1345 debug_cond(DEBUG_SETUP != 0,
1346 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1347 __func__, usb_ctrl->wValue);
1348 if (usb_ctrl->bRequestType
1349 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1350 break;
1351
1352 udc_set_address(dev, usb_ctrl->wValue);
1353 return;
1354
1355 case USB_REQ_SET_CONFIGURATION:
1356 debug_cond(DEBUG_SETUP != 0,
1357 "=====================================\n");
1358 debug_cond(DEBUG_SETUP != 0,
1359 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1360 __func__, usb_ctrl->wValue);
1361
1362 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1363 reset_available = 1;
1364
1365 break;
1366
1367 case USB_REQ_GET_DESCRIPTOR:
1368 debug_cond(DEBUG_SETUP != 0,
1369 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1370 __func__);
1371 break;
1372
1373 case USB_REQ_SET_INTERFACE:
1374 debug_cond(DEBUG_SETUP != 0,
1375 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1376 __func__, usb_ctrl->wValue);
1377
1378 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1379 reset_available = 1;
1380
1381 break;
1382
1383 case USB_REQ_GET_CONFIGURATION:
1384 debug_cond(DEBUG_SETUP != 0,
1385 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1386 __func__);
1387 break;
1388
1389 case USB_REQ_GET_STATUS:
1390 if (!dwc2_udc_get_status(dev, usb_ctrl))
1391 return;
1392
1393 break;
1394
1395 case USB_REQ_CLEAR_FEATURE:
1396 ep_num = usb_ctrl->wIndex & 0x7f;
1397
1398 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1399 return;
1400
1401 break;
1402
1403 case USB_REQ_SET_FEATURE:
1404 ep_num = usb_ctrl->wIndex & 0x7f;
1405
1406 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1407 return;
1408
1409 break;
1410
1411 default:
1412 debug_cond(DEBUG_SETUP != 0,
1413 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1414 "happened.\n", __func__, usb_ctrl->bRequest);
1415 break;
1416 }
1417 }
1418
1419
1420 if (likely(dev->driver)) {
1421
1422
1423 debug_cond(DEBUG_SETUP != 0,
1424 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1425 __func__);
1426
1427 spin_unlock(&dev->lock);
1428 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1429 spin_lock(&dev->lock);
1430
1431 if (i < 0) {
1432
1433 dwc2_udc_ep0_set_stall(ep);
1434 dev->ep0state = WAIT_FOR_SETUP;
1435
1436 debug_cond(DEBUG_SETUP != 0,
1437 "\tdev->driver->setup failed (%d),"
1438 " bRequest = %d\n",
1439 i, usb_ctrl->bRequest);
1440
1441
1442 } else if (dev->req_pending) {
1443 dev->req_pending = 0;
1444 debug_cond(DEBUG_SETUP != 0,
1445 "\tdev->req_pending...\n");
1446 }
1447
1448 debug_cond(DEBUG_SETUP != 0,
1449 "\tep0state = %s\n", state_names[dev->ep0state]);
1450
1451 }
1452}
1453
1454
1455
1456
1457static void dwc2_handle_ep0(struct dwc2_udc *dev)
1458{
1459 if (dev->ep0state == WAIT_FOR_SETUP) {
1460 debug_cond(DEBUG_OUT_EP != 0,
1461 "%s: WAIT_FOR_SETUP\n", __func__);
1462 dwc2_ep0_setup(dev);
1463
1464 } else {
1465 debug_cond(DEBUG_OUT_EP != 0,
1466 "%s: strange state!!(state = %s)\n",
1467 __func__, state_names[dev->ep0state]);
1468 }
1469}
1470
1471static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1472{
1473 debug_cond(DEBUG_EP0 != 0,
1474 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1475 if (ep_is_in(ep)) {
1476 dev->ep0state = DATA_STATE_XMIT;
1477 dwc2_ep0_write(dev);
1478
1479 } else {
1480 dev->ep0state = DATA_STATE_RECV;
1481 dwc2_ep0_read(dev);
1482 }
1483}
1484
