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7#ifndef __DWMMC_HW_H
8#define __DWMMC_HW_H
9
10#include <asm/io.h>
11#include <mmc.h>
12
13#define DWMCI_CTRL 0x000
14#define DWMCI_PWREN 0x004
15#define DWMCI_CLKDIV 0x008
16#define DWMCI_CLKSRC 0x00C
17#define DWMCI_CLKENA 0x010
18#define DWMCI_TMOUT 0x014
19#define DWMCI_CTYPE 0x018
20#define DWMCI_BLKSIZ 0x01C
21#define DWMCI_BYTCNT 0x020
22#define DWMCI_INTMASK 0x024
23#define DWMCI_CMDARG 0x028
24#define DWMCI_CMD 0x02C
25#define DWMCI_RESP0 0x030
26#define DWMCI_RESP1 0x034
27#define DWMCI_RESP2 0x038
28#define DWMCI_RESP3 0x03C
29#define DWMCI_MINTSTS 0x040
30#define DWMCI_RINTSTS 0x044
31#define DWMCI_STATUS 0x048
32#define DWMCI_FIFOTH 0x04C
33#define DWMCI_CDETECT 0x050
34#define DWMCI_WRTPRT 0x054
35#define DWMCI_GPIO 0x058
36#define DWMCI_TCMCNT 0x05C
37#define DWMCI_TBBCNT 0x060
38#define DWMCI_DEBNCE 0x064
39#define DWMCI_USRID 0x068
40#define DWMCI_VERID 0x06C
41#define DWMCI_HCON 0x070
42#define DWMCI_UHS_REG 0x074
43#define DWMCI_BMOD 0x080
44#define DWMCI_PLDMND 0x084
45#define DWMCI_DBADDR 0x088
46#define DWMCI_IDSTS 0x08C
47#define DWMCI_IDINTEN 0x090
48#define DWMCI_DSCADDR 0x094
49#define DWMCI_BUFADDR 0x098
50#define DWMCI_DATA 0x200
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53#define DWMCI_INTMSK_ALL 0xffffffff
54#define DWMCI_INTMSK_RE (1 << 1)
55#define DWMCI_INTMSK_CDONE (1 << 2)
56#define DWMCI_INTMSK_DTO (1 << 3)
57#define DWMCI_INTMSK_TXDR (1 << 4)
58#define DWMCI_INTMSK_RXDR (1 << 5)
59#define DWMCI_INTMSK_DCRC (1 << 7)
60#define DWMCI_INTMSK_RTO (1 << 8)
61#define DWMCI_INTMSK_DRTO (1 << 9)
62#define DWMCI_INTMSK_HTO (1 << 10)
63#define DWMCI_INTMSK_FRUN (1 << 11)
64#define DWMCI_INTMSK_HLE (1 << 12)
65#define DWMCI_INTMSK_SBE (1 << 13)
66#define DWMCI_INTMSK_ACD (1 << 14)
67#define DWMCI_INTMSK_EBE (1 << 15)
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69
70#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
71 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
72#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
73
74#define DWMCI_CTRL_RESET (1 << 0)
75#define DWMCI_CTRL_FIFO_RESET (1 << 1)
76#define DWMCI_CTRL_DMA_RESET (1 << 2)
77#define DWMCI_DMA_EN (1 << 5)
78#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
79#define DWMCI_IDMAC_EN (1 << 25)
80#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
81 DWMCI_CTRL_DMA_RESET)
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83
84#define DWMCI_CMD_RESP_EXP (1 << 6)
85#define DWMCI_CMD_RESP_LENGTH (1 << 7)
86#define DWMCI_CMD_CHECK_CRC (1 << 8)
87#define DWMCI_CMD_DATA_EXP (1 << 9)
88#define DWMCI_CMD_RW (1 << 10)
89#define DWMCI_CMD_SEND_STOP (1 << 12)
90#define DWMCI_CMD_ABORT_STOP (1 << 14)
91#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
92#define DWMCI_CMD_UPD_CLK (1 << 21)
93#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
94#define DWMCI_CMD_START (1 << 31)
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97#define DWMCI_CLKEN_ENABLE (1 << 0)
98#define DWMCI_CLKEN_LOW_PWR (1 << 16)
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101#define DWMCI_CTYPE_1BIT 0
102#define DWMCI_CTYPE_4BIT (1 << 0)
103#define DWMCI_CTYPE_8BIT (1 << 16)
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105
106#define DWMCI_BUSY (1 << 9)
107#define DWMCI_FIFO_MASK 0x1fff
108#define DWMCI_FIFO_SHIFT 17
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110
111#define MSIZE(x) ((x) << 28)
112#define RX_WMARK(x) ((x) << 16)
113#define TX_WMARK(x) (x)
114#define RX_WMARK_SHIFT 16
115#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
116
117#define DWMCI_IDMAC_OWN (1 << 31)
118#define DWMCI_IDMAC_CH (1 << 4)
119#define DWMCI_IDMAC_FS (1 << 3)
120#define DWMCI_IDMAC_LD (1 << 2)
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123#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
124#define DWMCI_BMOD_IDMAC_FB (1 << 1)
125#define DWMCI_BMOD_IDMAC_EN (1 << 7)
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127
128#define DWMCI_DDR_MODE (1 << 16)
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131#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
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149struct dwmci_host {
150 const char *name;
151 void *ioaddr;
152 unsigned int quirks;
153 unsigned int caps;
154 unsigned int version;
155 unsigned int clock;
156 unsigned int bus_hz;
157 unsigned int div;
158 int dev_index;
159 int dev_id;
160 int buswidth;
161 u32 fifoth_val;
162 struct mmc *mmc;
163 void *priv;
164
165 void (*clksel)(struct dwmci_host *host);
166 void (*board_init)(struct dwmci_host *host);
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181 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
182#ifndef CONFIG_BLK
183 struct mmc_config cfg;
184#endif
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187 bool fifo_mode;
188};
189
190struct dwmci_idmac {
191 u32 flags;
192 u32 cnt;
193 u32 addr;
194 u32 next_addr;
195} __aligned(ARCH_DMA_MINALIGN);
196
197static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
198{
199 writel(val, host->ioaddr + reg);
200}
201
202static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
203{
204 writew(val, host->ioaddr + reg);
205}
206
207static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
208{
209 writeb(val, host->ioaddr + reg);
210}
211static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
212{
213 return readl(host->ioaddr + reg);
214}
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216static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
217{
218 return readw(host->ioaddr + reg);
219}
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221static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
222{
223 return readb(host->ioaddr + reg);
224}
225
226#ifdef CONFIG_BLK
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259void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
260 u32 max_clk, u32 min_clk);
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277int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
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279#else
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290int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
291#endif
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293#ifdef CONFIG_DM_MMC
294
295int dwmci_probe(struct udevice *dev);
296extern const struct dm_mmc_ops dm_dwmci_ops;
297#endif
298
299#endif
300